Coverage for cuda / core / system / _clock.pxi: 32.61%

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1# SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 

2# 

3# SPDX-License-Identifier: Apache-2.0 

4  

5  

6_CLOCK_ID_MAPPING = { 

7 ClockId.CURRENT: nvml.ClockId.CURRENT, 

8 ClockId.CUSTOMER_BOOST_MAX: nvml.ClockId.CUSTOMER_BOOST_MAX, 

9} 

10  

11  

12_CLOCKS_EVENT_REASONS_MAPPING = { 

13 nvml.ClocksEventReasons.EVENT_REASON_NONE: ClocksEventReasons.NONE, 

14 nvml.ClocksEventReasons.EVENT_REASON_GPU_IDLE: ClocksEventReasons.GPU_IDLE, 

15 nvml.ClocksEventReasons.EVENT_REASON_APPLICATIONS_CLOCKS_SETTING: ClocksEventReasons.APPLICATIONS_CLOCKS_SETTING, 

16 nvml.ClocksEventReasons.EVENT_REASON_SW_POWER_CAP: ClocksEventReasons.SW_POWER_CAP, 

17 nvml.ClocksEventReasons.THROTTLE_REASON_HW_SLOWDOWN: ClocksEventReasons.HW_SLOWDOWN, 

18 nvml.ClocksEventReasons.EVENT_REASON_SYNC_BOOST: ClocksEventReasons.SYNC_BOOST, 

19 nvml.ClocksEventReasons.EVENT_REASON_SW_THERMAL_SLOWDOWN: ClocksEventReasons.SW_THERMAL_SLOWDOWN, 

20 nvml.ClocksEventReasons.THROTTLE_REASON_HW_THERMAL_SLOWDOWN: ClocksEventReasons.HW_THERMAL_SLOWDOWN, 

21 nvml.ClocksEventReasons.THROTTLE_REASON_HW_POWER_BRAKE_SLOWDOWN: ClocksEventReasons.HW_POWER_BRAKE_SLOWDOWN, 

22 nvml.ClocksEventReasons.EVENT_REASON_DISPLAY_CLOCK_SETTING: ClocksEventReasons.DISPLAY_CLOCK_SETTING, 

23} 

24  

25  

26_CLOCK_TYPE_MAPPING = { 

27 ClockType.GRAPHICS: nvml.ClockType.CLOCK_GRAPHICS, 

28 ClockType.SM: nvml.ClockType.CLOCK_SM, 

29 ClockType.MEMORY: nvml.ClockType.CLOCK_MEM, 

30 ClockType.VIDEO: nvml.ClockType.CLOCK_VIDEO, 

31} 

32  

33  

34cdef class ClockOffsets: 

35 """ 

36 Contains clock offset information. 

37 """ 

38  

39 cdef object _clock_offset 

40  

41 def __init__(self, clock_offset: nvml.ClockOffset): 

42 self._clock_offset = clock_offset 1a

43  

44 @property 

45 def clock_offset_mhz(self) -> int: 

46 """ 

47 The current clock offset in MHz. 

48 """ 

49 return self._clock_offset.clock_offset_m_hz 1a

50  

51 @property 

52 def max_offset_mhz(self) -> int: 

53 """ 

54 The maximum clock offset in MHz. 

55 """ 

56 return self._clock_offset.max_clock_offset_m_hz 1a

57  

58 @property 

59 def min_offset_mhz(self) -> int: 

60 """ 

61 The minimum clock offset in MHz. 

62 """ 

63 return self._clock_offset.min_clock_offset_m_hz 1a

64  

65  

66cdef class ClockInfo: 

67 """ 

68 Accesses various clock information about a device. 

69 """ 

70  

71 cdef intptr_t _handle 

72 cdef int _clock_type 

73  

74 def __init__(self, handle, clock_type: ClockType | str): 

75 self._handle = handle 1a

76 try: 1a

77 clock_type = _CLOCK_TYPE_MAPPING[clock_type] 1a

78 except KeyError: 

79 raise ValueError( 

80 f"Invalid clock type: {clock_type}. " 

81 f"Must be one of {list(ClockType.__members__.values())}" 

82 ) from None 

83 self._clock_type = int(clock_type) 1a

84  

85 def get_current_mhz(self, clock_id: ClockId | str = ClockId.CURRENT) -> int: 

86 """ 

87 Get the current clock speed of a specific clock domain, in MHz. 

88  

89 For Kepler™ or newer fully supported devices. 

90  

91 Parameters 

92 ---------- 

93 clock_id: :class:`ClockId` | str 

94 The clock ID to query. Defaults to the current clock value. 

95  

96 Returns 

97 ------- 

98 int 

99 The clock speed in MHz. 

100 """ 

101 try: 1a

102 clock_id = _CLOCK_ID_MAPPING[clock_id] 1a

103 except KeyError: 

104 raise ValueError( 

105 f"Invalid clock ID: {clock_id}. " 

106 f"Must be one of {list(ClockId.__members__.values())}" 

107 ) from None 

108 return nvml.device_get_clock(self._handle, self._clock_type, clock_id) 1a

109  

110 def get_max_mhz(self) -> int: 

111 """ 

112 Get the maximum clock speed of a specific clock domain, in MHz. 

113  

114 For Fermi™ or newer fully supported devices. 

115  

116 Current P0 clocks (reported by :meth:`get_current_mhz` can differ from 

117 max clocks by a few MHz. 

118  

119 Returns 

120 ------- 

121 int 

122 The maximum clock speed in MHz. 

123 """ 

124 return nvml.device_get_max_clock_info(self._handle, self._clock_type) 1a

125  

126 def get_max_customer_boost_mhz(self) -> int: 

127 """ 

128 Get the maximum customer boost clock speed of a specific clock, in MHz. 

129  

130 For Pascal™ or newer fully supported devices. 

131  

132 Returns 

133 ------- 

134 int 

135 The maximum customer boost clock speed in MHz. 

136 """ 

137 return nvml.device_get_max_customer_boost_clock(self._handle, self._clock_type) 1a

138  

139 def get_min_max_clock_of_pstate_mhz(self, pstate: int) -> tuple[int, int]: 

140 """ 

141 Get the minimum and maximum clock speeds for this clock domain 

142 at a given performance state (Pstate), in MHz. 

143  

144 Parameters 

145 ---------- 

146 pstate: int 

147 The performance state to query. Must be an int between 0 and 15, 

148 where 0 is the highest performance state (P0) and 15 is the lowest 

149 (P15). 

150  

151 Returns 

152 ------- 

153 tuple[int, int] 

154 A tuple containing the minimum and maximum clock speeds in MHz. 

155 """ 

156 return nvml.device_get_min_max_clock_of_p_state(self._handle, self._clock_type, _pstate_to_enum(pstate)) 1a

157  

158 def get_offsets(self, pstate: int) -> ClockOffsets: 

159 """ 

160 Retrieve min, max and current clock offset of some clock domain for a given Pstate. 

161  

162 For Maxwell™ or newer fully supported devices. 

163  

164 Parameters 

165 ---------- 

166 pstate: int 

167 The performance state to query. Must be an int between 0 and 15, 

168 where 0 is the highest performance state (P0) and 15 is the lowest 

169 (P15). 

170  

171 Returns 

172 ------- 

173 :obj:`~_device.ClockOffsets` 

174 An object with the min, max and current clock offset. 

175 """ 

176 return ClockOffsets(nvml.device_get_clock_offsets(self._handle, self._clock_type, _pstate_to_enum(pstate))) 1a