Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.

Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
--------------------------------------------------------------------------------

#define NV_PFAULT_FAULT_TYPE_PDE                  0x00000000 /*       */
#define NV_PFAULT_FAULT_TYPE_PDE_SIZE             0x00000001 /*       */
#define NV_PFAULT_FAULT_TYPE_PTE                  0x00000002 /*       */
#define NV_PFAULT_FAULT_TYPE_VA_LIMIT_VIOLATION   0x00000003 /*       */
#define NV_PFAULT_FAULT_TYPE_UNBOUND_INST_BLOCK   0x00000004 /*       */
#define NV_PFAULT_FAULT_TYPE_PRIV_VIOLATION       0x00000005 /*       */
#define NV_PFAULT_FAULT_TYPE_RO_VIOLATION         0x00000006 /*       */
#define NV_PFAULT_FAULT_TYPE_WO_VIOLATION         0x00000007 /*       */
#define NV_PFAULT_FAULT_TYPE_PITCH_MASK_VIOLATION 0x00000008 /*       */
#define NV_PFAULT_FAULT_TYPE_WORK_CREATION        0x00000009 /*       */
#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_APERTURE 0x0000000a /*       */
#define NV_PFAULT_FAULT_TYPE_COMPRESSION_FAILURE  0x0000000b /*       */
#define NV_PFAULT_FAULT_TYPE_UNSUPPORTED_KIND     0x0000000c /*       */
#define NV_PFAULT_FAULT_TYPE_REGION_VIOLATION     0x0000000d /*       */
#define NV_PFAULT_FAULT_TYPE_POISONED             0x0000000e /*       */
#define NV_PFAULT_FAULT_TYPE_ATOMIC_VIOLATION     0x0000000f /*       */
#define NV_PFAULT_ACCESS_TYPE_READ       0x00000000 /*       */
#define NV_PFAULT_ACCESS_TYPE_WRITE      0x00000001 /*       */
#define NV_PFAULT_ACCESS_TYPE_ATOMIC     0x00000002 /*       */
#define NV_PFAULT_ACCESS_TYPE_PREFETCH   0x00000003 /*       */
#define NV_PFAULT_ACCESS_TYPE_VIRT_READ          0x00000000 /*       */
#define NV_PFAULT_ACCESS_TYPE_VIRT_WRITE         0x00000001 /*       */
#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC        0x00000002 /*       */
#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_STRONG 0x00000002 /*       */
#define NV_PFAULT_ACCESS_TYPE_VIRT_PREFETCH      0x00000003 /*       */
#define NV_PFAULT_ACCESS_TYPE_VIRT_ATOMIC_WEAK   0x00000004 /*       */
#define NV_PFAULT_ACCESS_TYPE_PHYS_READ          0x00000008 /*       */
#define NV_PFAULT_ACCESS_TYPE_PHYS_WRITE         0x00000009 /*       */
#define NV_PFAULT_ACCESS_TYPE_PHYS_ATOMIC        0x0000000a /*       */
#define NV_PFAULT_ACCESS_TYPE_PHYS_PREFETCH      0x0000000b /*       */
#define NV_PFAULT_MMU_CLIENT_TYPE_GPC    0x00000000 /*       */
#define NV_PFAULT_MMU_CLIENT_TYPE_HUB    0x00000001 /*       */

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                         KEY LEGEND
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Each define in the .ref file has a 5 field code to say what kind of define it is: i.e. /* RW--R */
The following legend shows accepted values for each of the 5 fields:
  Read, Write, Internal State, Declaration/Size, and Define Indicator.

  Read
    ' ' = Other Information
    '-' = Field is part of a write-only register
    'C' = Value read is always the same, constant value line follows (C)
    'R' = Value is read


  Write
    ' ' = Other Information
    '-' = Must not be written (D), value ignored when written (R,A,F)
    'W' = Can be written


  Internal State
    ' ' = Other Information
    '-' = No internal state
    'X' = Internal state, initial value is unknown
    'I' = Internal state, initial value is known and follows (I), see "Reset Signal" section for signal.
    'E' = Internal state, initial value is known and follows (E), see "Reset Signal" section for signal.
    'B' = Internal state, initial value is known and follows (B), see "Reset Signal" section for signal.
    'C' = Internal state, initial value is known and follows (C), see "Reset Signal" section for signal.

    'V' = (legacy) Internal state, initialize at volatile reset
    'D' = (legacy) Internal state, default initial value at object creation (legacy: Only used in dev_ram.ref)
    'C' = (legacy) Internal state, initial value at object creation
    'C' = (legacy) Internal state, class-based initial value at object creation (legacy: Only used in dev_ram.ref)


  Declaration/Size
    ' ' = Other Information
    '-' = Does Not Apply
    'V' = Type is void
    'U' = Type is unsigned integer
    'S' = Type is signed integer
    'F' = Type is IEEE floating point
    '1' = Byte size (008)
    '2' = Short size (016)
    '3' = Three byte size (024)
    '4' = Word size (032)
    '8' = Double size (064)


  Define Indicator
    ' ' = Other Information
    'C' = Clear value
    'D' = Device
    'L' = Logical device.
    'M' = Memory
    'R' = Register
    'A' = Array of Registers
    'F' = Field
    'V' = Value
    'T' = Task
    'P' = Phantom Register

    'B' = (legacy) Bundle address
    'G' = (legacy) General purpose configuration register
    'C' = (legacy) Class

  Reset signal defaults for graphics engine registers.
    All graphics engine registers use the following defaults for reset signals:
     'E' = initialized with engine_reset_
     'I' = initialized with context_reset_
     'B' = initialized with reset_IB_dly_

  Reset signal
    For units that differ from the graphics engine defaults, the reset signals should be defined here: