Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.

Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
the rights to use, copy, modify, merge, publish, distribute, sublicense,
and/or sell copies of the Software, and to permit persons to whom the
Software is furnished to do so, subject to the following conditions:

The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.

THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
DEALINGS IN THE SOFTWARE.
--------------------------------------------------------------------------------

#define NV_PCFG                             0x00088FFF:0x00088000 /* RW--D */
#define NV_XVE                              0x00000FFF:0x00000000 /* RW--D */
#define NV_XVE_ID                            0x00000000 /* R--4R */
#define NV_XVE_ID_VENDOR                           15:0 /* C--VF */
#define NV_XVE_ID_VENDOR_NVIDIA              0x000010DE /* C---V */
#define NV_XVE_ID_DEVICE_CHIP                     31:16 /* R-CVF */
#define NV_XVE_ID_DEVICE_CHIP_NO_USE         0x00000000 /* R-C-V */
#define NV_XVE_ID_DEVICE_CHIP_NV30           0x00000300 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_NV31           0x00000320 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_NV34           0x00000380 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_NV35           0x000003A0 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_NV40           0x00000040 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_NV41           0x000000C0 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_NV42           0x00000120 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_NV43           0x00000140 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_NV44           0x00000160 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_NV46           0x000001D0 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_NV47           0x00000090 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_G74            0x00000480 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_NV50           0x00000190 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_G84            0x00000400 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_G82            0x00000410 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_G86            0x00000420 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_G88            0x00000430 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_G92            0x00000600 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_G94            0x00000620 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_G96            0x00000640 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GT200          0x000005E0 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_G98            0x000006E0 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_IGT206         0x00000AE0 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_IGT209         0x00000B00 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GT212          0x00000A00 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GT214          0x000006A0 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GT216          0x00000A20 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GT218          0x00000A60 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GF100          0x000006C0 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GF102          0x00000D00 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GF103          0x00000D20 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GF104          0x00000E20 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GF105          0x00000DA0 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GF106          0x00000DC0 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GF108          0x00000DE0 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GF110D         0x00000CC0 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GF110F         0x00000CE0 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GF117          0x00001140 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GK104          0x00001180 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GK106          0x000011C0 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GK107          0x00000FC0 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GK110          0x00001000 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GK208          0x00001280 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GM108          0x00001340 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GM107          0x00001380 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GM104          0x00001580 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GM204          0x000013C0 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GM206          0x00001400 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GM200          0x000017C0 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GP100          0x000015C0 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GP102          0x00001B00 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GP104          0x00001B80 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GP106          0x00001C00 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GP107          0x00001C80 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GP108          0x00001D00 /* R---V */
#define NV_XVE_ID_DEVICE_CHIP_GV100          0x00001D80 /* R---V */
#define NV_XVE_DEV_CTRL                                        0x00000004 /* RW-4R */
#define NV_XVE_DEV_CTRL_CMD_IO_SPACE                                   0:0 /* RWIVF */
#define NV_XVE_DEV_CTRL_CMD_IO_SPACE_DISABLED                   0x00000000 /* RWI-V */
#define NV_XVE_DEV_CTRL_CMD_IO_SPACE_ENABLED                    0x00000001 /* RW--V */
#define NV_XVE_DEV_CTRL_CMD_MEMORY_SPACE                               1:1 /* RWIVF */
#define NV_XVE_DEV_CTRL_CMD_MEMORY_SPACE_DISABLED               0x00000000 /* RWI-V */
#define NV_XVE_DEV_CTRL_CMD_MEMORY_SPACE_ENABLED                0x00000001 /* RW--V */
#define NV_XVE_DEV_CTRL_CMD_BUS_MASTER                                 2:2 /* RWIVF */
#define NV_XVE_DEV_CTRL_CMD_BUS_MASTER_DISABLED                 0x00000000 /* RWI-V */
#define NV_XVE_DEV_CTRL_CMD_BUS_MASTER_ENABLED                  0x00000001 /* RW--V */
#define NV_XVE_DEV_CTRL_CMD_SPECIAL_CYCLE                              3:3 /* C--VF */
#define NV_XVE_DEV_CTRL_CMD_SPECIAL_CYCLE_DISABLED              0x00000000 /* C---V */
#define NV_XVE_DEV_CTRL_CMD_MEM_WRITE_AND_INVALIDATE                   4:4 /* C--VF */
#define NV_XVE_DEV_CTRL_CMD_MEM_WRITE_AND_INVALIDATE_DISABLED   0x00000000 /* C---V */
#define NV_XVE_DEV_CTRL_CMD_VGA_PALETTE_SNOOP                          5:5 /* C--VF */
#define NV_XVE_DEV_CTRL_CMD_VGA_PALETTE_SNOOP_DISABLED          0x00000000 /* C---V */
#define NV_XVE_DEV_CTRL_CMD_PERR                                       6:6 /* RWIVF */
#define NV_XVE_DEV_CTRL_CMD_PERR_DISABLED                       0x00000000 /* RWI-V */
#define NV_XVE_DEV_CTRL_CMD_PERR_ENABLED                        0x00000001 /* RW--V */
#define NV_XVE_DEV_CTRL_CMD_IDSEL_STEP                                 7:7 /* C--VF */
#define NV_XVE_DEV_CTRL_CMD_IDSEL_STEP_DISABLED                 0x00000000 /* C---V */
#define NV_XVE_DEV_CTRL_CMD_SERR                                       8:8 /* RWIVF */
#define NV_XVE_DEV_CTRL_CMD_SERR_DISABLED                       0x00000000 /* RWI-V */
#define NV_XVE_DEV_CTRL_CMD_SERR_ENABLED                        0x00000001 /* RW--V */
#define NV_XVE_DEV_CTRL_CMD_FAST_BACK2BACK                             9:9 /* C--VF */
#define NV_XVE_DEV_CTRL_CMD_FAST_BACK2BACK_DISABLED             0x00000000 /* C---V */
#define NV_XVE_DEV_CTRL_CMD_INTERRUPT_DISABLE                        10:10 /* RWIVF */
#define NV_XVE_DEV_CTRL_CMD_INTERRUPT_DISABLE_INIT              0x00000000 /* RWI-V */
#define NV_XVE_DEV_CTRL_STAT_INTERRUPT                               19:19 /* R-IVF */
#define NV_XVE_DEV_CTRL_STAT_INTERRUPT_NOT_PENDING              0x00000000 /* R-I-V */
#define NV_XVE_DEV_CTRL_STAT_INTERRUPT_PENDING                  0x00000001 /* R---V */
#define NV_XVE_DEV_CTRL_STAT_CAPLIST                                 20:20 /* C--VF */
#define NV_XVE_DEV_CTRL_STAT_CAPLIST_NOT_PRESENT                0x00000000 /* ----V */
#define NV_XVE_DEV_CTRL_STAT_CAPLIST_PRESENT                    0x00000001 /* C---V */
#define NV_XVE_DEV_CTRL_STAT_66MHZ                                   21:21 /* C--VF */
#define NV_XVE_DEV_CTRL_STAT_66MHZ_INCAPABLE                    0x00000000 /* C---V */
#define NV_XVE_DEV_CTRL_STAT_66MHZ_CAPABLE                      0x00000001 /* ----V */
#define NV_XVE_DEV_CTRL_STAT_FAST_BACK2BACK                          23:23 /* C--VF */
#define NV_XVE_DEV_CTRL_STAT_FAST_BACK2BACK_INCAPABLE           0x00000000 /* C---V */
#define NV_XVE_DEV_CTRL_STAT_FAST_BACK2BACK_CAPABLE             0x00000001 /* ----V */
#define NV_XVE_DEV_CTRL_STAT_MASTER_DATA_PERR                        24:24 /* RWIVF */
#define NV_XVE_DEV_CTRL_STAT_MASTER_DATA_PERR_ACTIVE            0x00000001 /* R---V */
#define NV_XVE_DEV_CTRL_STAT_MASTER_DATA_PERR_NOT_ACTIVE        0x00000000 /* R-I-V */
#define NV_XVE_DEV_CTRL_STAT_MASTER_DATA_PERR_CLEAR             0x00000001 /* -W--C */
#define NV_XVE_DEV_CTRL_STAT_DEVSEL_TIMING                           26:25 /* C--VF */
#define NV_XVE_DEV_CTRL_STAT_DEVSEL_TIMING_FAST                 0x00000000 /* C---V */
#define NV_XVE_DEV_CTRL_STAT_DEVSEL_TIMING_MEDIUM               0x00000001 /* ----V */
#define NV_XVE_DEV_CTRL_STAT_DEVSEL_TIMING_SLOW                 0x00000002 /* ----V */
#define NV_XVE_DEV_CTRL_STAT_SIGNALED_TARGET_ABORT                   27:27 /* RWIVF */
#define NV_XVE_DEV_CTRL_STAT_SIGNALED_TARGET_ABORT_NO           0x00000000 /* R-I-V */
#define NV_XVE_DEV_CTRL_STAT_SIGNALED_TARGET_ABORT_YES          0x00000001 /* R---V */
#define NV_XVE_DEV_CTRL_STAT_SIGNALED_TARGET_ABORT_CLEAR        0x00000001 /* -W--C */
#define NV_XVE_DEV_CTRL_STAT_RECEIVED_TARGET_ABORT                   28:28 /* RWIVF */
#define NV_XVE_DEV_CTRL_STAT_RECEIVED_TARGET_ABORT_NO           0x00000000 /* R-I-V */
#define NV_XVE_DEV_CTRL_STAT_RECEIVED_TARGET_ABORT_YES          0x00000001 /* R---V */
#define NV_XVE_DEV_CTRL_STAT_RECEIVED_TARGET_ABORT_CLEAR        0x00000001 /* -W--C */
#define NV_XVE_DEV_CTRL_STAT_RECEIVED_MASTER_ABORT                   29:29 /* RWIVF */
#define NV_XVE_DEV_CTRL_STAT_RECEIVED_MASTER_ABORT_NO           0x00000000 /* R-I-V */
#define NV_XVE_DEV_CTRL_STAT_RECEIVED_MASTER_ABORT_YES          0x00000001 /* R---V */
#define NV_XVE_DEV_CTRL_STAT_RECEIVED_MASTER_ABORT_CLEAR        0x00000001 /* -W--C */
#define NV_XVE_DEV_CTRL_STAT_SIGNALED_SERR                           30:30 /* RWIVF */
#define NV_XVE_DEV_CTRL_STAT_SIGNALED_SERR_NOT_ACTIVE           0x00000000 /* R-I-V */
#define NV_XVE_DEV_CTRL_STAT_SIGNALED_SERR_ACTIVE               0x00000001 /* R---V */
#define NV_XVE_DEV_CTRL_STAT_SIGNALED_SERR_CLEAR                0x00000001 /* -W--C */
#define NV_XVE_DEV_CTRL_STAT_DETECTED_PERR                           31:31 /* RWIVF */
#define NV_XVE_DEV_CTRL_STAT_DETECTED_PERR_NOT_ACTIVE           0x00000000 /* R-I-V */
#define NV_XVE_DEV_CTRL_STAT_DETECTED_PERR_ACTIVE               0x00000001 /* R---V */
#define NV_XVE_DEV_CTRL_STAT_DETECTED_PERR_CLEAR                0x00000001 /* -W--C */
#define NV_XVE_REV_ID                                 0x00000008 /* R--4R */
#define NV_XVE_REV_ID_FIB                                    3:0 /* R-CVF */
#define NV_XVE_REV_ID_FIB_ONE                         0x00000001 /* R-C-V */
#define NV_XVE_REV_ID_FIB_TWO                         0x00000002 /* R---V */
#define NV_XVE_REV_ID_MASK                                   7:4 /* R-CVF */
#define NV_XVE_REV_ID_MASK_A                          0x0000000A /* R-C-V */
#define NV_XVE_REV_ID_MASK_B                          0x0000000B /* ----V */
#define NV_XVE_REV_ID_CLASS_CODE                            31:8 /* R-CVF */
#define NV_XVE_REV_ID_CLASS_CODE_VGA                  0x00030000 /* R-C-V */
#define NV_XVE_REV_ID_CLASS_CODE_3D                   0x00030200 /* ----V */
#define NV_XVE_REV_ID_CLASS_CODE_MULTIMEDIA           0x00048000 /* ----V */
#define NV_XVE_MISC_1                                        0x0000000C /* RW-4R */
#define NV_XVE_MISC_1_CACHE_LINE_SIZE                               7:0 /* RWIVF */
#define NV_XVE_MISC_1_CACHE_LINE_SIZE_INIT                   0x00000000 /* RWI-V */
#define NV_XVE_MISC_1_MASTER_LATENCY_TIMER                        15:11 /* C--VF */
#define NV_XVE_MISC_1_MASTER_LATENCY_TIMER_0_CLOCKS          0x00000000 /* C---V */
#define NV_XVE_MISC_1_HEADER_TYPE                                 23:16 /* R-IVF */
#define NV_XVE_MISC_1_HEADER_TYPE_SINGLEFUNC                 0x00000000 /* R-I-V */
#define NV_XVE_MISC_1_HEADER_TYPE_MULTIFUNC                  0x00000080 /* R---V */
#define NV_XVE_BAR0                                 0x00000010 /* RW-4R */
#define NV_XVE_BAR0_SPACE_TYPE                             0:0 /* C--VF */
#define NV_XVE_BAR0_SPACE_TYPE_MEMORY               0x00000000 /* C---V */
#define NV_XVE_BAR0_SPACE_TYPE_IO                   0x00000001 /* ----V */
#define NV_XVE_BAR0_ADDRESS_TYPE                           2:1 /* C--VF */
#define NV_XVE_BAR0_ADDRESS_TYPE_32_BIT             0x00000000 /* C---V */
#define NV_XVE_BAR0_ADDRESS_TYPE_20_BIT             0x00000001 /* ----V */
#define NV_XVE_BAR0_ADDRESS_TYPE_64_BIT             0x00000002 /* ----V */
#define NV_XVE_BAR0_PREFETCHABLE                           3:3 /* C--VF */
#define NV_XVE_BAR0_PREFETCHABLE_NOT                0x00000000 /* C---V */
#define NV_XVE_BAR0_PREFETCHABLE_MERGABLE           0x00000001 /* ----V */
#define NV_XVE_BAR0_BASE_ADDRESS                         31:24 /* RWIVF */
#define NV_XVE_BAR0_BASE_ADDRESS_INIT               0x00000000 /* RWI-V */
#define NV_XVE_BAR1_LO                                 0x00000014 /* RW-4R */
#define NV_XVE_BAR1_LO_SPACE_TYPE                             0:0 /* C--VF */
#define NV_XVE_BAR1_LO_SPACE_TYPE_MEMORY               0x00000000 /* C---V */
#define NV_XVE_BAR1_LO_SPACE_TYPE_IO                   0x00000001 /* ----V */
#define NV_XVE_BAR1_LO_ADDRESS_TYPE                           2:1 /* C--VF */
#define NV_XVE_BAR1_LO_ADDRESS_TYPE_32_BIT             0x00000000 /* ----V */
#define NV_XVE_BAR1_LO_ADDRESS_TYPE_20_BIT             0x00000001 /* ----V */
#define NV_XVE_BAR1_LO_ADDRESS_TYPE_64_BIT             0x00000002 /* C---V */
#define NV_XVE_BAR1_LO_PREFETCHABLE                           3:3 /* C--VF */
#define NV_XVE_BAR1_LO_PREFETCHABLE_NOT                0x00000000 /* ----V */
#define NV_XVE_BAR1_LO_PREFETCHABLE_MERGABLE           0x00000001 /* C---V */
#define NV_XVE_BAR1_LO_BASE_ADDRESS                         31:26 /* RWIVF */
#define NV_XVE_BAR1_LO_BASE_ADDRESS_INIT               0x00000000 /* RWI-V */
#define NV_XVE_BAR1_HI                                 0x00000018 /* RW-4R */
#define NV_XVE_BAR1_HI_BASE_ADDRESS                          31:0 /* RWIVF */
#define NV_XVE_BAR1_HI_BASE_ADDRESS_INIT               0x00000000 /* RWI-V */
#define NV_XVE_BAR2_LO                                 0x0000001C /* RW-4R */
#define NV_XVE_BAR2_LO_SPACE_TYPE                             0:0 /* C--VF */
#define NV_XVE_BAR2_LO_SPACE_TYPE_MEMORY               0x00000000 /* C---V */
#define NV_XVE_BAR2_LO_SPACE_TYPE_IO                   0x00000001 /* ----V */
#define NV_XVE_BAR2_LO_ADDRESS_TYPE                           2:1 /* C--VF */
#define NV_XVE_BAR2_LO_ADDRESS_TYPE_32_BIT             0x00000000 /* ----V */
#define NV_XVE_BAR2_LO_ADDRESS_TYPE_20_BIT             0x00000001 /* ----V */
#define NV_XVE_BAR2_LO_ADDRESS_TYPE_64_BIT             0x00000002 /* C---V */
#define NV_XVE_BAR2_LO_PREFETCHABLE                           3:3 /* C--VF */
#define NV_XVE_BAR2_LO_PREFETCHABLE_NOT                0x00000000 /* ----V */
#define NV_XVE_BAR2_LO_PREFETCHABLE_MERGABLE           0x00000001 /* C---V */
#define NV_XVE_BAR2_LO_BASE_ADDRESS                         31:24 /* RWIVF */
#define NV_XVE_BAR2_LO_BASE_ADDRESS_INIT               0x00000000 /* RWI-V */
#define NV_XVE_BAR2_HI                                 0x00000020 /* RW-4R */
#define NV_XVE_BAR2_HI_BASE_ADDRESS                          31:0 /* RWIVF */
#define NV_XVE_BAR2_HI_BASE_ADDRESS_INIT               0x00000000 /* RWI-V */
#define NV_XVE_BAR3                                 0x00000024 /* RW-4R */
#define NV_XVE_BAR3_SPACE_TYPE                             0:0 /* R-IVF */
#define NV_XVE_BAR3_SPACE_TYPE_MEMORY               0x00000000 /* ----V */
#define NV_XVE_BAR3_SPACE_TYPE_IO                   0x00000001 /* R-I-V */
#define NV_XVE_BAR3_ADDRESS_TYPE                           2:1 /* R-IVF */
#define NV_XVE_BAR3_ADDRESS_TYPE_32_BIT             0x00000000 /* R-I-V */
#define NV_XVE_BAR3_ADDRESS_TYPE_20_BIT             0x00000001 /* ----V */
#define NV_XVE_BAR3_ADDRESS_TYPE_64_BIT             0x00000002 /* ----V */
#define NV_XVE_BAR3_PREFETCHABLE                           3:3 /* R-IVF */
#define NV_XVE_BAR3_PREFETCHABLE_NOT                0x00000000 /* R-I-V */
#define NV_XVE_BAR3_PREFETCHABLE_MERGABLE           0x00000001 /* ----V */
#define NV_XVE_BAR3_BASE_ADDRESS                          31:7 /* RWIVF */
#define NV_XVE_BAR3_BASE_ADDRESS_INIT               0x00000000 /* RWI-V */
#define NV_XVE_SUBSYSTEM                      0x0000002C /* R--4R */
#define NV_XVE_SUBSYSTEM_VENDOR_ID                  15:0 /* R-CVF */
#define NV_XVE_SUBSYSTEM_VENDOR_ID_NONE       0x00000000 /* R-C-V */
#define NV_XVE_SUBSYSTEM_ID_USER                   19:16 /* R-CVF */
#define NV_XVE_SUBSYSTEM_ID_USER_NONE         0x00000000 /* R-C-V */
#define NV_XVE_SUBSYSTEM_ID_NON_USER               31:20 /* R-CVF */
#define NV_XVE_SUBSYSTEM_ID_NON_USER_NONE     0x00000000 /* R-C-V */
#define NV_XVE_ROM                            0x00000030 /* RW-4R */
#define NV_XVE_ROM_DECODE                            0:0 /* RWIVF */
#define NV_XVE_ROM_DECODE_DISABLED            0x00000000 /* RWI-V */
#define NV_XVE_ROM_DECODE_ENABLED             0x00000001 /* RW--V */
#define NV_XVE_ROM_BASE                            31:16 /* RWIVF */
#define NV_XVE_ROM_BASE_INIT                  0x00000000 /* RWI-V */
#define NV_XVE_CAP_LIST                                0x00000034 /* C--4R */
#define NV_XVE_CAP_LIST_CAP_PTR                               7:0 /* C--VF */
#define NV_XVE_CAP_LIST_CAP_PTR_POWER_MGMT             0x00000060 /* C---V */
#define NV_XVE_INTR_GNT                                0x0000003C /* RW-4R */
#define NV_XVE_INTR_GNT_INTR_LINE                             7:0 /* RWIVF */
#define NV_XVE_INTR_GNT_INTR_LINE_IRQ0                 0x00000000 /* RWI-V */
#define NV_XVE_INTR_GNT_INTR_LINE_IRQ1                 0x00000001 /* RW--V */
#define NV_XVE_INTR_GNT_INTR_LINE_IRQ15                0x0000000F /* RW--V */
#define NV_XVE_INTR_GNT_INTR_LINE_UNKNOWN              0x000000FF /* RW--V */
#define NV_XVE_INTR_GNT_INTR_PIN                             15:8 /* C--VF */
#define NV_XVE_INTR_GNT_INTR_PIN_INTA                  0x00000001 /* C---V */
#define NV_XVE_INTR_GNT_MIN_GNT                             23:16 /* C--VF */
#define NV_XVE_INTR_GNT_MIN_GNT_NO_REQUIREMENTS        0x00000000 /* C---V */
#define NV_XVE_INTR_GNT_MAX_LAT                             31:24 /* C--VF */
#define NV_XVE_INTR_GNT_MAX_LAT_NO_REQUIREMENTS        0x00000000 /* C---V */
#define NV_XVE_PWR_MGMT_0                                0x00000060 /* R--4R */
#define NV_XVE_PWR_MGMT_0_PME_D3_COLD                         31:31 /* R-IVF */
#define NV_XVE_PWR_MGMT_0_PME_D3_COLD_SUPPORTED          0x00000001 /* ----V */
#define NV_XVE_PWR_MGMT_0_PME_D3_COLD_NOT_SUPPORTED      0x00000000 /* R-I-V */
#define NV_XVE_PWR_MGMT_0_PME_D3_HOT                          30:30 /* R-IVF */
#define NV_XVE_PWR_MGMT_0_PME_D3_HOT_SUPPORTED           0x00000001 /* ----V */
#define NV_XVE_PWR_MGMT_0_PME_D3_HOT_NOT_SUPPORTED       0x00000000 /* R-I-V */
#define NV_XVE_PWR_MGMT_0_PME_D2                              29:29 /* R-IVF */
#define NV_XVE_PWR_MGMT_0_PME_D2_SUPPORTED               0x00000001 /* ----V */
#define NV_XVE_PWR_MGMT_0_PME_D2_NOT_SUPPORTED           0x00000000 /* R-I-V */
#define NV_XVE_PWR_MGMT_0_PME_D1                              28:28 /* R-IVF */
#define NV_XVE_PWR_MGMT_0_PME_D1_SUPPORTED               0x00000001 /* ----V */
#define NV_XVE_PWR_MGMT_0_PME_D1_NOT_SUPPORTED           0x00000000 /* R-I-V */
#define NV_XVE_PWR_MGMT_0_PME_D0                              27:27 /* R-IVF */
#define NV_XVE_PWR_MGMT_0_PME_D0_SUPPORTED               0x00000001 /* ----V */
#define NV_XVE_PWR_MGMT_0_PME_D0_NOT_SUPPORTED           0x00000000 /* R-I-V */
#define NV_XVE_PWR_MGMT_0_D2                                  26:26 /* R-IVF */
#define NV_XVE_PWR_MGMT_0_D2_SUPPORTED                   0x00000001 /* ----V */
#define NV_XVE_PWR_MGMT_0_D2_NOT_SUPPORTED               0x00000000 /* R-I-V */
#define NV_XVE_PWR_MGMT_0_D1                                  25:25 /* R-IVF */
#define NV_XVE_PWR_MGMT_0_D1_SUPPORTED                   0x00000001 /* ----V */
#define NV_XVE_PWR_MGMT_0_D1_NOT_SUPPORTED               0x00000000 /* R-I-V */
#define NV_XVE_PWR_MGMT_0_DSI                                 21:21 /* R-IVF */
#define NV_XVE_PWR_MGMT_0_DSI_NOT_REQUIRED               0x00000000 /* R-I-V */
#define NV_XVE_PWR_MGMT_0_PME_CLOCK                           19:19 /* R-IVF */
#define NV_XVE_PWR_MGMT_0_PME_CLOCK_NOT_REQUIRED         0x00000000 /* R-I-V */
#define NV_XVE_PWR_MGMT_0_VERSION                             18:16 /* C--VF */
#define NV_XVE_PWR_MGMT_0_VERSION_1                      0x00000001 /* ----V */
#define NV_XVE_PWR_MGMT_0_VERSION_2                      0x00000002 /* ----V */
#define NV_XVE_PWR_MGMT_0_VERSION_3                      0x00000003 /* C---V */
#define NV_XVE_PWR_MGMT_0_NEXT_PTR                             15:8 /* C--VF */
#define NV_XVE_PWR_MGMT_0_NEXT_PTR_NULL                  0x00000000 /* ----V */
#define NV_XVE_PWR_MGMT_0_NEXT_PTR_MSI                   0x00000068 /* C---V */
#define NV_XVE_PWR_MGMT_0_CAP_ID                                7:0 /* C--VF */
#define NV_XVE_PWR_MGMT_0_CAP_ID_POWER_MGMT              0x00000001 /* C---V */
#define NV_XVE_PWR_MGMT_1                                   0x00000064 /* RW-4R */
#define NV_XVE_PWR_MGMT_1_PME_DATA                               31:24 /* C--VF */
#define NV_XVE_PWR_MGMT_1_PME_DATA_UNS                      0x00000000 /* C---V */
#define NV_XVE_PWR_MGMT_1_PME_BPCC                               23:23 /* C--VF */
#define NV_XVE_PWR_MGMT_1_PME_BPCC_UNS                      0x00000000 /* C---V */
#define NV_XVE_PWR_MGMT_1_PME_B2B3                               22:22 /* C--VF */
#define NV_XVE_PWR_MGMT_1_PME_B2B3_UNS                      0x00000000 /* C---V */
#define NV_XVE_PWR_MGMT_1_PME_STATUS                             15:15 /* RWIVF */
#define NV_XVE_PWR_MGMT_1_PME_STATUS_NOT_ACTIVE             0x00000000 /* R-I-V */
#define NV_XVE_PWR_MGMT_1_PME_STATUS_ACTIVE                 0x00000001 /* R---V */
#define NV_XVE_PWR_MGMT_1_PME_STATUS_CLEAR                  0x00000001 /* -W--C */
#define NV_XVE_PWR_MGMT_1_PME_DATA_SCALE                         14:13 /* C--VF */
#define NV_XVE_PWR_MGMT_1_PME_DATA_SCALE_UNS                0x00000000 /* C---V */
#define NV_XVE_PWR_MGMT_1_PME_DATA_SEL                            12:9 /* C--VF */
#define NV_XVE_PWR_MGMT_1_PME_DATA_SEL_UNS                  0x00000000 /* C---V */
#define NV_XVE_PWR_MGMT_1_PME                                      8:8 /* RWIVF */
#define NV_XVE_PWR_MGMT_1_PME_DISABLE                       0x00000000 /* RWI-V */
#define NV_XVE_PWR_MGMT_1_PME_ENABLE                        0x00000001 /* RW--V */
#define NV_XVE_PWR_MGMT_1_NO_SOFT_RESET                            3:3 /* R-IVF */
#define NV_XVE_PWR_MGMT_1_NO_SOFT_RESET_ENABLE              0x00000001 /* R-I-V */
#define NV_XVE_PWR_MGMT_1_NO_SOFT_RESET_DISABLE             0x00000000 /* R---V */
#define NV_XVE_PWR_MGMT_1_PWR_STATE                                1:0 /* RWIVF */
#define NV_XVE_PWR_MGMT_1_PWR_STATE_D0                      0x00000000 /* RWI-V */
#define NV_XVE_PWR_MGMT_1_PWR_STATE_D1                      0x00000001 /* RW--V */
#define NV_XVE_PWR_MGMT_1_PWR_STATE_D2                      0x00000002 /* RW--V */
#define NV_XVE_PWR_MGMT_1_PWR_STATE_D3HOT                   0x00000003 /* RW--V */
#define NV_XVE_MSI_CTRL                                    0x00000068 /* RW-4R */
#define NV_XVE_MSI_CTRL_RSVD                                    31:24 /* C--VF */
#define NV_XVE_MSI_CTRL_RSVD_0                             0x00000000 /* C---V */
#define NV_XVE_MSI_CTRL_64BIT_CAP                               23:23 /* R-IVF */
#define NV_XVE_MSI_CTRL_64BIT_CAP_TRUE                     0x00000001 /* R-I-V */
#define NV_XVE_MSI_CTRL_64BIT_CAP_FALSE                    0x00000000 /* R---V */
#define NV_XVE_MSI_CTRL_MULT_EN                                 22:20 /* RWIVF */
#define NV_XVE_MSI_CTRL_MULT_EN_CODE0                      0x00000000 /* RWI-V */
#define NV_XVE_MSI_CTRL_MULT_EN_CODE2                      0x00000001 /* RW--V */
#define NV_XVE_MSI_CTRL_MULT_EN_CODE4                      0x00000002 /* RW--V */
#define NV_XVE_MSI_CTRL_MULT_EN_CODE8                      0x00000003 /* RW--V */
#define NV_XVE_MSI_CTRL_MULT_CAP                                19:17 /* R-IVF */
#define NV_XVE_MSI_CTRL_MULT_CAP_CODE0                     0x00000000 /* R-I-V */
#define NV_XVE_MSI_CTRL_MSI                                     16:16 /* RWIVF */
#define NV_XVE_MSI_CTRL_MSI_DISABLE                        0x00000000 /* RWI-V */
#define NV_XVE_MSI_CTRL_MSI_ENABLE                         0x00000001 /* RW--V */
#define NV_XVE_MSI_CTRL_NEXT_PTR                                 15:8 /* C--VF */
#define NV_XVE_MSI_CTRL_NEXT_PTR_PCIEXP                    0x00000078 /* C---V */
#define NV_XVE_MSI_CTRL_CAP_ID                                    7:0 /* C--VF */
#define NV_XVE_MSI_CTRL_CAP_ID_MSI                         0x00000005 /* C---V */
#define NV_XVE_DEVICE_CAPABILITY                                        0x0000007C /* R--4R */
#define NV_XVE_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE                              2:0 /* R-IVF */
#define NV_XVE_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_INIT                  0x00000001 /* R-I-V */
#define NV_XVE_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_128B                  0x00000000 /* R---V */
#define NV_XVE_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_256B                  0x00000001 /* R---V */
#define NV_XVE_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_512B                  0x00000002 /* R---V */
#define NV_XVE_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_1024B                 0x00000003 /* R---V */
#define NV_XVE_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_2048B                 0x00000004 /* R---V */
#define NV_XVE_DEVICE_CAPABILITY_MAX_PAYLOAD_SIZE_4096B                 0x00000005 /* R---V */
#define NV_XVE_DEVICE_CAPABILITY_PHANTOM_FUNCTIONS_SUPPORTED                   4:3 /* C--VF */
#define NV_XVE_DEVICE_CAPABILITY_PHANTOM_FUNCTIONS_SUPPORTED_INIT       0x00000000 /* C---V */
#define NV_XVE_DEVICE_CAPABILITY_EXTENDED_TAG_FIELD_SIZE                       5:5 /* R-IVF */
#define NV_XVE_DEVICE_CAPABILITY_EXTENDED_TAG_FIELD_SIZE_INIT           0x00000001 /* R-I-V */
#define NV_XVE_DEVICE_CAPABILITY_ENDPOINT_L0S_ACCEPTABLE_LATENCY               8:6 /* R-XVF */
#define NV_XVE_DEVICE_CAPABILITY_ENDPOINT_L1_ACCEPTABLE_LATENCY               11:9 /* R-XVF */
#define NV_XVE_DEVICE_CAPABILITY_RSVD                                        14:12 /* C--VF */
#define NV_XVE_DEVICE_CAPABILITY_RSVD_INIT                              0x00000000 /* C---V */
#define NV_XVE_DEVICE_CAPABILITY_ROLE_BASED_ERR_REPORTING                    15:15 /* C--VF */
#define NV_XVE_DEVICE_CAPABILITY_ROLE_BASED_ERR_REPORTING_INIT          0x00000001 /* C---V */
#define NV_XVE_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_VALUE             25:18 /* R-IVF */
#define NV_XVE_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_VALUE_INIT   0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_SCALE             27:26 /* R-IVF */
#define NV_XVE_DEVICE_CAPABILITY_CAPTURED_SLOT_POWER_LIMIT_SCALE_INIT   0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET                        28:28 /* C--VF */
#define NV_XVE_DEVICE_CAPABILITY_FUNCTION_LEVEL_RESET_NOT_SUPPORTED     0x00000000 /* C---V */
#define NV_XVE_DEVICE_CONTROL_STATUS                                        0x00000080 /* RWI4R */
#define NV_XVE_DEVICE_CONTROL_STATUS_CORR_ERROR_REPORTING_ENABLE                   0:0 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_CORR_ERROR_REPORTING_ENABLE_INIT       0x00000000 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_REPORTING_ENABLE              1:1 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_REPORTING_ENABLE_INIT  0x00000000 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_FATAL_ERROR_REPORTING_ENABLE                  2:2 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_FATAL_ERROR_REPORTING_ENABLE_INIT      0x00000000 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_UNSUPP_REQ_REPORTING_ENABLE                   3:3 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_UNSUPP_REQ_REPORTING_ENABLE_INIT       0x00000000 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING                       4:4 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_ENABLE_RELAXED_ORDERING_INIT           0x00000001 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE                              7:5 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_INIT                  0x00000000 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_128B                  0x00000000 /* R---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_256B                  0x00000001 /* R---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_512B                  0x00000002 /* R---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_1024B                 0x00000003 /* R---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_2048B                 0x00000004 /* R---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_PAYLOAD_SIZE_4096B                 0x00000005 /* R---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE                     8:8 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE_INIT         0x00000001 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_EXTENDED_TAG_FIELD_ENABLE_ENABLED      0x00000001 /* RW--V */
#define NV_XVE_DEVICE_CONTROL_STATUS_PHANTOM_FUNCTIONS_ENABLE                      9:9 /* R-IVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_PHANTOM_FUNCTIONS_ENABLE_INIT          0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_AUXILLARY_POWER_PM_ENABLE                   10:10 /* R-IVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_AUXILLARY_POWER_PM_ENABLE_INIT         0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_ENABLE_NO_SNOOP                             11:11 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_ENABLE_NO_SNOOP_INIT                   0x00000001 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_READ_REQUEST_SIZE                       14:12 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_MAX_READ_REQUEST_SIZE_INIT             0x00000002 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_RSVD                                        15:15 /* C--VF */
#define NV_XVE_DEVICE_CONTROL_STATUS_RSVD_INIT                              0x00000000 /* C---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED                         16:16 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED_INIT               0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_CORR_ERROR_DETECTED_CLEAR              0x00000001 /* -W--C */
#define NV_XVE_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED                    17:17 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED_INIT          0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_NON_FATAL_ERROR_DETECTED_CLEAR         0x00000001 /* -W--C */
#define NV_XVE_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED                        18:18 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED_INIT              0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_FATAL_ERROR_DETECTED_CLEAR             0x00000001 /* -W--C */
#define NV_XVE_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED                     19:19 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED_INIT           0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_UNSUPP_REQUEST_DETECTED_CLEAR          0x00000001 /* -W--C */
#define NV_XVE_DEVICE_CONTROL_STATUS_AUX_POWER_DETECTED                          20:20 /* R-IVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_AUX_POWER_DETECTED_INIT                0x00000000 /* R-I-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_TRANSACTIONS_PENDING                        21:21 /* R-IVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_TRANSACTIONS_PENDING_INIT              0x00000000 /* R-I-V */
#define NV_XVE_LINK_CAPABILITIES                                             0x00000084 /* R--4R */
#define NV_XVE_LINK_CAPABILITIES_MAX_LINK_SPEED                                     3:0 /* R-XVF */
#define NV_XVE_LINK_CAPABILITIES_MAX_LINK_WIDTH                                     9:4 /* R-XVF */
#define NV_XVE_LINK_CAPABILITIES_ACTIVE_STATE_LINK_PM_SUPPORT                     11:10 /* R-IVF */
#define NV_XVE_LINK_CAPABILITIES_ACTIVE_STATE_LINK_PM_SUPPORT_INIT           0x00000003 /* R-I-V */
#define NV_XVE_LINK_CAPABILITIES_L0S_EXIT_LATENCY                                 14:12 /* R-XVF */
#define NV_XVE_LINK_CAPABILITIES_L1_EXIT_LATENCY                                  17:15 /* R-XVF */
#define NV_XVE_LINK_CAPABILITIES_CLOCK_PM                                         18:18 /* R-IVF */
#define NV_XVE_LINK_CAPABILITIES_CLOCK_PM_INIT                               0x00000000 /* R-I-V */
#define NV_XVE_LINK_CAPABILITIES_CLOCK_PM_DISABLE                            0x00000000 /* R---V */
#define NV_XVE_LINK_CAPABILITIES_CLOCK_PM_ENABLE                             0x00000001 /* R---V */
#define NV_XVE_LINK_CAPABILITIES_SURPRISE_DOWN_ERROR_REPORTING                    19:19 /* C--VF */
#define NV_XVE_LINK_CAPABILITIES_SURPRISE_DOWN_ERROR_REPORTING_NOT_SUPPORTED 0x00000000 /* C---V */
#define NV_XVE_LINK_CAPABILITIES_DLL_ACTIVE_REPORTING                             20:20 /* C--VF */
#define NV_XVE_LINK_CAPABILITIES_DLL_ACTIVE_REPORTING_NOT_SUPPORTED          0x00000000 /* C---V */
#define NV_XVE_LINK_CAPABILITIES_LINK_BANDWIDTH_NOTIFICATION                      21:21 /* C--VF */
#define NV_XVE_LINK_CAPABILITIES_LINK_BANDWIDTH_NOTIFICATION_NOT_SUPPORTED   0x00000000 /* C---V */
#define NV_XVE_LINK_CAPABILITIES_ASPM_OPTIONALITY_COMPLIANCE                      22:22 /* R-I-F */
#define NV_XVE_LINK_CAPABILITIES_ASPM_OPTIONALITY_COMPLIANCE_SUPPORTED       0x00000001 /* R-I-V */
#define NV_XVE_LINK_CAPABILITIES_ASPM_OPTIONALITY_COMPLIANCE_NOT_SUPPORTED   0x00000000 /* R---V */
#define NV_XVE_LINK_CAPABILITIES_PORT_NUMBER                                      31:24 /* R-XVF */
#define NV_XVE_LINK_CONTROL_STATUS                                                              0x00000088 /* RWI4R */
#define NV_XVE_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL                                        1:0 /* RWIVF */
#define NV_XVE_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_INIT                            0x00000000 /* RWI-V */
#define NV_XVE_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_L1_DISABLE_L0S_DISABLE          0x00000000 /* RW--V */
#define NV_XVE_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_L1_DISABLE_L0S_ENABLE           0x00000001 /* RW--V */
#define NV_XVE_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_L1_ENABLE_L0S_DISABLE           0x00000002 /* RW--V */
#define NV_XVE_LINK_CONTROL_STATUS_ACTIVE_STATE_LINK_PM_CONTROL_L1_ENABLE_L0S_ENABLE            0x00000003 /* RW--V */
#define NV_XVE_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY                                            3:3 /* RWIVF */
#define NV_XVE_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY_INIT                                0x00000000 /* RWI-V */
#define NV_XVE_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY_64B                                 0x00000000 /* RW--V */
#define NV_XVE_LINK_CONTROL_STATUS_READ_COMPLETION_BOUNDARY_128B                                0x00000001 /* RW--V */
#define NV_XVE_LINK_CONTROL_STATUS_LINK_DISABLE                                                        4:4 /* C--VF */
#define NV_XVE_LINK_CONTROL_STATUS_LINK_DISABLE_INIT                                            0x00000000 /* C---V */
#define NV_XVE_LINK_CONTROL_STATUS_RETRAIN_LINK                                                        5:5 /* C--VF */
#define NV_XVE_LINK_CONTROL_STATUS_RETRAIN_LINK_INIT                                            0x00000000 /* C---V */
#define NV_XVE_LINK_CONTROL_STATUS_COMMON_CLOCK_CONFIGURATION                                          6:6 /* RWIVF */
#define NV_XVE_LINK_CONTROL_STATUS_COMMON_CLOCK_CONFIGURATION_INIT                              0x00000000 /* RWI-V */
#define NV_XVE_LINK_CONTROL_STATUS_EXTENDED_SYNCH                                                      7:7 /* RWIVF */
#define NV_XVE_LINK_CONTROL_STATUS_EXTENDED_SYNCH_INIT                                          0x00000000 /* RWI-V */
#define NV_XVE_LINK_CONTROL_STATUS_CLOCK_PM                                                            8:8 /* RWIVF */
#define NV_XVE_LINK_CONTROL_STATUS_CLOCK_PM_INIT                                                0x00000000 /* RWI-V */
#define NV_XVE_LINK_CONTROL_STATUS_HW_AUTO_WIDTH_DISABLE                                               9:9 /* RWIVF */
#define NV_XVE_LINK_CONTROL_STATUS_HW_AUTO_WIDTH_DISABLE_INIT                                   0x00000000 /* RWI-V */
#define NV_XVE_LINK_CONTROL_STATUS_LINK_BANDWIDTH_MANAGEMENT_INTR_EN                                 10:10 /* C--VF */
#define NV_XVE_LINK_CONTROL_STATUS_LINK_BANDWIDTH_MANAGEMENT_INTR_EN_INIT                       0x00000000 /* C---V */
#define NV_XVE_LINK_CONTROL_STATUS_LINK_AUTO_BANDWIDTH_INTR_EN                                       11:11 /* C--VF */
#define NV_XVE_LINK_CONTROL_STATUS_LINK_AUTO_BANDWIDTH_INTR_EN_INIT                             0x00000000 /* C---V */
#define NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED                                                        19:16 /* R--VF */
#define NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_2P5                                               0x00000001 /* R---V */
#define NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_5P0                                               0x00000002 /* R---V */
#define NV_XVE_LINK_CONTROL_STATUS_LINK_SPEED_8P0                                               0x00000003 /* R---V */
#define NV_XVE_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH                                             25:20 /* R--VF */
#define NV_XVE_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X1                                     0x00000001 /* R---V */
#define NV_XVE_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X2                                     0x00000002 /* R---V */
#define NV_XVE_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X4                                     0x00000004 /* R---V */
#define NV_XVE_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X8                                     0x00000008 /* R---V */
#define NV_XVE_LINK_CONTROL_STATUS_NEGOTIATED_LINK_WIDTH_X16                                    0x00000010 /* R---V */
#define NV_XVE_LINK_CONTROL_STATUS_RSVD                                                              26:26 /* C--VF */
#define NV_XVE_LINK_CONTROL_STATUS_RSVD_INIT                                                    0x00000000 /* C---V */
#define NV_XVE_LINK_CONTROL_STATUS_LINK_TRAINING                                                     27:27 /* R-IVF */
#define NV_XVE_LINK_CONTROL_STATUS_LINK_TRAINING_INIT                                           0x00000000 /* R-I-V */
#define NV_XVE_LINK_CONTROL_STATUS_SLOT_CLOCK_CONFIGURATON                                           28:28 /* R-IVF */
#define NV_XVE_LINK_CONTROL_STATUS_SLOT_CLOCK_CONFIGURATON_INIT                                    0x00000001 /* R-I-V */
#define NV_XVE_LINK_CONTROL_STATUS_DLL_ACTIVE                                                        29:29 /* R-IVF */
#define NV_XVE_LINK_CONTROL_STATUS_DLL_ACTIVE_INIT                                            0x00000000 /* R-I-V */
#define NV_XVE_LINK_CONTROL_STATUS_LINK_BANDWIDTH_MANAGEMENT                                         30:30 /* C--VF */
#define NV_XVE_LINK_CONTROL_STATUS_LINK_BANDWIDTH_MANAGEMENT_INIT                            0x00000000 /* C---V */
#define NV_XVE_LINK_CONTROL_STATUS_LINK_AUTO_BANDWIDTH                                               31:31 /* C--VF */
#define NV_XVE_LINK_CONTROL_STATUS_LINK_AUTO_BANDWIDTH_INIT                                    0x00000000 /* C---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2                                         0x000000A0 /* RWI4R */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES                             3:0 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_A_LO           0x00000001 /* RW--V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_A_HI           0x00000002 /* RW--V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_B_LO           0x00000005 /* RW--V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_B_HI           0x00000006 /* RW--V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_RANGES_RANGE_DEFAULT        0x00000000 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE                            4:4 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE_ENABLED             0x00000000 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE_DISABLED            0x00000001 /* RW--V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_CPL_TIMEOUT_DISABLE_GEN2_PROTO_DISABLED 0x00000000 /* RW--V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_ARI_FORWARDING_ENABLE                          5:5 /* C--VF */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_ARI_FORWARDING_ENABLE_INIT              0x00000000 /* C---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_REQUESTER_ENABLE                     6:6 /* C--VF */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_REQUESTER_ENABLE_INIT         0x00000000 /* C---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_EGRESS_BLOCKING                      7:7 /* C--VF */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_ATOMIC_OP_EGRESS_BLOCKING_INIT          0x00000000 /* C---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_IDO_REQUEST_ENABLE                             8:8 /* C--VF */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_IDO_REQUEST_ENABLE_INIT                 0x00000000 /* C---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_IDO_COMPLETION_ENABLE                          9:9 /* C--VF */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_IDO_COMPLETION_ENABLE_INIT              0x00000000 /* C---V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_LTR_ENABLE                                   10:10 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_LTR_ENABLE_INIT                         0x00000000 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_LTR_ENABLE_DISABLED                     0x00000000 /* RW--V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_LTR_ENABLE_ENABLED                      0x00000001 /* RW--V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_OBFF_ENABLE                                  14:13 /* RWIVF */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_OBFF_ENABLE_DISABLED                    0x00000000 /* RWI-V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_OBFF_ENABLE_MSG_SGNL_VA                 0x00000001 /* RW--V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_OBFF_ENABLE_MSG_SGNL_VB                 0x00000002 /* RW--V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_OBFF_ENABLE_WAKE_SGNL                   0x00000003 /* RW--V */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_BITS                                         31:15 /* C--VF */
#define NV_XVE_DEVICE_CONTROL_STATUS_2_BITS_0                                  0x00000000 /* C---V */
#define NV_XVE_LINK_CAPABILITIES_2                                            0x000000A4 /* R-I4R */
#define NV_XVE_LINK_CAPABILITIES_2_RSVD                                              0:0 /* C--VF */
#define NV_XVE_LINK_CAPABILITIES_2_RSVD_INIT                                  0x00000000 /* C---V */
#define NV_XVE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED                              7:1 /* R-IVF */
#define NV_XVE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_HIDDEN                0x00000000 /* R---V */
#define NV_XVE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1                  0x00000001 /* R---V */
#define NV_XVE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2             0x00000003 /* R---V */
#define NV_XVE_LINK_CAPABILITIES_2_SUPPORTED_LINK_SPEED_GEN1_GEN2_GEN3        0x00000007 /* R-I-V */
#define NV_XVE_LINK_CAPABILITIES_2_CROSS_LINK_SUPPORT                                8:8 /* C--VF */
#define NV_XVE_LINK_CAPABILITIES_2_CROSS_LINK_SUPPORT_DISABLED                0x00000000 /* C---V */
#define NV_XVE_LINK_CAPABILITIES_2_EMBEDDED_LINK                                     9:9 /* R-IVF */
#define NV_XVE_LINK_CAPABILITIES_2_EMBEDDED_LINK_PRESENT                      0x00000001 /* R-I-V */
#define NV_XVE_LINK_CAPABILITIES_2_EMBEDDED_LINK_NOT_PRESENT                  0x00000000 /* R---V */
#define NV_XVE_LINK_CAPABILITIES_2_EP_FLT                                          10:10 /* R-IVF */
#define NV_XVE_LINK_CAPABILITIES_2_EP_FLT_SUPPORTED                           0x00000001 /* R-I-V */
#define NV_XVE_LINK_CAPABILITIES_2_EP_FLT_NOT_SUPPORTED                       0x00000000 /* R---V */
#define NV_XVE_LINK_CAPABILITIES_2_BURST_TRAINING                                  11:11 /* R-IVF */
#define NV_XVE_LINK_CAPABILITIES_2_BURST_TRAINING_SUPPORTED                   0x00000001 /* R---V */
#define NV_XVE_LINK_CAPABILITIES_2_BURST_TRAINING_NOT_SUPPORTED               0x00000000 /* R-I-V */
#define NV_XVE_LINK_CAPABILITIES_2_SCRATCH                                         31:12 /* R-IVF */
#define NV_XVE_LINK_CAPABILITIES_2_SCRATCH_INIT                               0x00000000 /* R-I-V */
#define NV_XVE_LINK_CONTROL_STATUS_2                                            0x000000A8 /* RWI4R */
#define NV_XVE_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED                                 3:0 /* RWCVF */
#define NV_XVE_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED_GEN2_PROTO_DISABLED      0x00000000 /* RW--V */
#define NV_XVE_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED_2P5                      0x00000001 /* RW--V */
#define NV_XVE_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED_5P0                      0x00000002 /* RW--V */
#define NV_XVE_LINK_CONTROL_STATUS_2_TARGET_LINK_SPEED_8P0                      0x00000003 /* RWC-V */
#define NV_XVE_LINK_CONTROL_STATUS_2_ENTER_COMPLIANCE                                  4:4 /* RWCVF */
#define NV_XVE_LINK_CONTROL_STATUS_2_ENTER_COMPLIANCE_GEN2_PROTO_DISABLED       0x00000000 /* RW--V */
#define NV_XVE_LINK_CONTROL_STATUS_2_ENTER_COMPLIANCE_INIT                      0x00000000 /* RWC-V */
#define NV_XVE_LINK_CONTROL_STATUS_2_HW_AUTO_SPEED_DISABLE                             5:5 /* RWCVF */
#define NV_XVE_LINK_CONTROL_STATUS_2_HW_AUTO_SPEED_DISABLE_GEN2_PROTO_DISABLED  0x00000000 /* RW--V */
#define NV_XVE_LINK_CONTROL_STATUS_2_HW_AUTO_SPEED_DISABLE_INIT                 0x00000000 /* RWC-V */
#define NV_XVE_LINK_CONTROL_STATUS_2_RVSD                                              6:6 /* C--VF */
#define NV_XVE_LINK_CONTROL_STATUS_2_RVSD_0                                     0x00000000 /* C---V */
#define NV_XVE_LINK_CONTROL_STATUS_2_TRANSMIT_MARGIN                                   9:7 /* RWCVF */
#define NV_XVE_LINK_CONTROL_STATUS_2_TRANSMIT_MARGIN_INIT                       0x00000000 /* RWC-V */
#define NV_XVE_LINK_CONTROL_STATUS_2_ENTER_MOD_COMPLIANCE                            10:10 /* RWCVF */
#define NV_XVE_LINK_CONTROL_STATUS_2_ENTER_MOD_COMPLIANCE_INIT                  0x00000000 /* RWC-V */
#define NV_XVE_LINK_CONTROL_STATUS_2_COMPLIANCE_SOS                                  11:11 /* RWCVF */
#define NV_XVE_LINK_CONTROL_STATUS_2_COMPLIANCE_SOS_INIT                        0x00000000 /* RWC-V */
#define NV_XVE_LINK_CONTROL_STATUS_2_COMPLIANCE_PRESET_DEEMPHASIS                    15:12 /* RWCVF */
#define NV_XVE_LINK_CONTROL_STATUS_2_COMPLIANCE_PRESET_DEEMPHASIS_INIT          0x00000000 /* RWC-V */
#define NV_XVE_LINK_CONTROL_STATUS_2_CUR_DEEMPHASIS_LEVEL                            16:16 /* R--VF */
#define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_COMPLETE                           17:17 /* R-CVF */
#define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_COMPLETE_NOT_DONE             0x00000000 /* R-C-V */
#define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_COMPLETE_DONE                 0x00000001 /* R---V */
#define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE1_SUCCESSFUL                  18:18 /* R-CVF */
#define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE1_SUCCESSFUL_NOT_DONE    0x00000000 /* R-C-V */
#define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE1_SUCCESSFUL_DONE        0x00000001 /* R---V */
#define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE2_SUCCESSFUL                  19:19 /* R-CVF */
#define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE2_SUCCESSFUL_NOT_DONE    0x00000000 /* R-C-V */
#define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE2_SUCCESSFUL_DONE        0x00000001 /* R---V */
#define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE3_SUCCESSFUL                  20:20 /* R-CVF */
#define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE3_SUCCESSFUL_NOT_DONE    0x00000000 /* R-C-V */
#define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_PHASE3_SUCCESSFUL_DONE        0x00000001 /* R---V */
#define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_REQUEST                            21:21 /* RWCVF */
#define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_REQUEST_NOT_SET               0x00000000 /* R-C-V */
#define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_REQUEST_SET                   0x00000001 /* R---V */
#define NV_XVE_LINK_CONTROL_STATUS_2_EQUALIZATION_REQUEST_CLEAR                 0x00000001 /* -W--V */
#define NV_XVE_LINK_CONTROL_STATUS_2_RP_FLT                                          22:22 /* RWIVF */
#define NV_XVE_LINK_CONTROL_STATUS_2_RP_FLT_SUPPORTED                           0x00000001 /* RW--V */
#define NV_XVE_LINK_CONTROL_STATUS_2_RP_FLT_NOT_SUPPORTED                       0x00000000 /* RWI-V */
#define NV_XVE_LINK_CONTROL_STATUS_2_HAS_TRAINED                                     23:23 /* RWIVF */
#define NV_XVE_LINK_CONTROL_STATUS_2_HAS_TRAINED_YES                            0x00000001 /* RW--V */
#define NV_XVE_LINK_CONTROL_STATUS_2_HAS_TRAINED_NO                             0x00000000 /* RWI-V */
#define NV_XVE_LINK_CONTROL_STATUS_2_BURST_TRAINING                                  24:24 /* RWIVF */
#define NV_XVE_LINK_CONTROL_STATUS_2_BURST_TRAINING_YES                         0x00000001 /* RW--V */
#define NV_XVE_LINK_CONTROL_STATUS_2_BURST_TRAINING_NO                          0x00000000 /* RWI-V */
#define NV_XVE_LINK_CONTROL_STATUS_2_SCRATCH                                         31:25 /* RWIVF */
#define NV_XVE_LINK_CONTROL_STATUS_2_SCRATCH_INIT                               0x00000000 /* RWI-V */
#define NV_XVE_VENDOR_SPECIFIC_MSGBOX_COMMAND                               0x000000B8 /* RW-4R */
#define NV_XVE_VENDOR_SPECIFIC_MSGBOX_COMMAND_INTR                               31:31 /* RWIVF */
#define NV_XVE_VENDOR_SPECIFIC_MSGBOX_COMMAND_INTR_INIT                     0x00000000 /* R-I-V */
#define NV_XVE_VENDOR_SPECIFIC_MSGBOX_COMMAND_BITS                                30:0 /* RWIVF */
#define NV_XVE_VENDOR_SPECIFIC_MSGBOX_COMMAND_BITS_INIT                     0x00000000 /* R-I-V */
#define NV_XVE_VENDOR_SPECIFIC_MSGBOX_DATA_IN                               0x000000BC /* RW-4R */
#define NV_XVE_VENDOR_SPECIFIC_MSGBOX_DATA_IN_BITS                                31:0 /* RWIVF */
#define NV_XVE_VENDOR_SPECIFIC_MSGBOX_DATA_IN_BITS_INIT                     0x00000000 /* R-I-V */
#define NV_XVE_VENDOR_SPECIFIC_MSGBOX_DATA_OUT                              0x000000C0 /* RW-4R */
#define NV_XVE_VENDOR_SPECIFIC_MSGBOX_DATA_OUT_BITS                               31:0 /* RWIVF */
#define NV_XVE_VENDOR_SPECIFIC_MSGBOX_DATA_OUT_BITS_INIT                    0x00000000 /* R-I-V */
#define NV_XVE_VENDOR_SPECIFIC_MSGBOX_MUTEX                                 0x000000C4 /* RWI4R */
#define NV_XVE_VENDOR_SPECIFIC_MSGBOX_MUTEX_BITS                                   7:0 /* RWIVF */
#define NV_XVE_VENDOR_SPECIFIC_MSGBOX_MUTEX_BITS_INIT                       0x00000000 /* RWI-V */
#define NV_XVE_VENDOR_SPECIFIC_MSGBOX_MUTEX_RSVD                                  31:8 /* C--VF */
#define NV_XVE_VENDOR_SPECIFIC_MSGBOX_MUTEX_RSVD_0                          0x00000000 /* C---V */
#define NV_XVE_LINK_CAPABILITIES_OVERRIDE                                     0x000000F0 /* RW-4R */
#define NV_XVE_LINK_CAPABILITIES_OVERRIDE_ASPM_WRITE                                 0:0 /* RWCVF */
#define NV_XVE_LINK_CAPABILITIES_OVERRIDE_ASPM_WRITE_DISABLED                 0x00000000 /* RWC-V */
#define NV_XVE_LINK_CAPABILITIES_OVERRIDE_ASPM_WRITE_ENABLED                  0x00000001 /* RW--V */
#define NV_XVE_LINK_CAPABILITIES_OVERRIDE_ASPM_READ                                  1:1 /* RWCVF */
#define NV_XVE_LINK_CAPABILITIES_OVERRIDE_ASPM_READ_DISABLED                  0x00000000 /* RWC-V */
#define NV_XVE_LINK_CAPABILITIES_OVERRIDE_ASPM_READ_ENABLED                   0x00000001 /* RW--V */
#define NV_XVE_VCCAP_HDR                                 0x00000100 /* R--4R */
#define NV_XVE_VCCAP_HDR_ID                                    15:0 /* C--VF */
#define NV_XVE_VCCAP_HDR_ID_VC                           0x00000002 /* C---V */
#define NV_XVE_VCCAP_HDR_VER                                  19:16 /* C--VF */
#define NV_XVE_VCCAP_HDR_VER_1                           0x00000001 /* C---V */
#define NV_XVE_VCCAP_HDR_NXT                                  31:20 /* R--VF */
#define NV_XVE_VCCAP_HDR_NXT_PWR_BUDGET                  0x00000128 /* R---V */
#define NV_XVE_VCCAP_HDR_NXT_LTR                         0x00000250 /* R---V */
#define NV_XVE_VCCAP_HDR_NXT_L1_SUBSTATES                0x00000258 /* R---V */
#define NV_XVE_PRIV_XV_TIMEOUT                                  0x00000144 /* RW-4R */
#define NV_XVE_PRIV_XV_TIMEOUT_MILLISECOND                             7:0 /* RWCVF */
#define NV_XVE_PRIV_XV_TIMEOUT_MILLISECOND_16                   0x00000010 /* RWC-V */
#define NV_XVE_PRIV_XV_TIMEOUT_DISABLE                                 8:8 /* RWCVF */
#define NV_XVE_PRIV_XV_TIMEOUT_DISABLE_INIT                     0x00000000 /* RWC-V */
#define NV_XVE_PRIV_XV_TIMEOUT_RSVD_MERGER_NP                        19:16 /* C--VF */
#define NV_XVE_PRIV_XV_TIMEOUT_RSVD_MERGER_NP_INIT              0x00000000 /* C---V */
#define NV_XVE_PRIV_XV_TIMEOUT_RSVD_MERGER_PW                        23:20 /* C--VF */
#define NV_XVE_PRIV_XV_TIMEOUT_RSVD_MERGER_PW_INIT              0x00000000 /* C---V */
#define NV_XVE_PRIV_XV_TIMEOUT_OVERRIDE                              24:24 /* RWCVF */
#define NV_XVE_PRIV_XV_TIMEOUT_OVERRIDE_INIT                    0x00000000 /* RWC-V */
#define NV_XVE_PRIV_XV_TIMEOUT_OVERRIDE_ENABLE                  0x00000001 /* RW--V */
#define NV_XVE_PRIV_XV_TIMEOUT_OVERRIDE_DISABLE                 0x00000000 /* RW--V */
#define NV_XVE_PRIV_MISC                                         0x0000014C /* RW-4R */
#define NV_XVE_PRIV_MISC_RSVD_WRR_NUM_CLK_PHASE                        15:0 /* C--VF */
#define NV_XVE_PRIV_MISC_RSVD_WRR_NUM_CLK_PHASE_INIT             0x0000001B /* C---V */
#define NV_XVE_PRIV_MISC_RSVD_NUM_NPT_VC1                             20:16 /* C--VF */
#define NV_XVE_PRIV_MISC_RSVD_NUM_NPT_VC1_INIT                   0x00000000 /* C---V */
#define NV_XVE_PRIV_MISC_CYA_NOT_USE_TC0_NON_COHERENT                 21:21 /* RWCVF */
#define NV_XVE_PRIV_MISC_CYA_NOT_USE_TC0_NON_COHERENT_INIT       0x00000000 /* RWC-V */
#define NV_XVE_PRIV_MISC_RSVD_CYA_SINGLE_FUNC                         22:22 /* C--VF */
#define NV_XVE_PRIV_MISC_RSVD_CYA_SINGLE_FUNC_INIT               0x00000000 /* C---V */
#define NV_XVE_PRIV_MISC_CYA_IGNORE_POISONED_WDATA                    23:23 /* RWCVF */
#define NV_XVE_PRIV_MISC_CYA_IGNORE_POISONED_WDATA_INIT          0x00000000 /* RWC-V */
#define NV_XVE_PRIV_MISC_COHERENT_RELAXED_ORDERING                    24:24 /* RWCVF */
#define NV_XVE_PRIV_MISC_COHERENT_RELAXED_ORDERING_INIT          0x00000001 /* RWC-V */
#define NV_XVE_PRIV_MISC_NON_COHERENT_RELAXED_ORDERING                25:25 /* RWCVF */
#define NV_XVE_PRIV_MISC_NON_COHERENT_RELAXED_ORDERING_INIT      0x00000001 /* RWC-V */
#define NV_XVE_PRIV_MISC_CYA_GPU_DL_UP                                26:26 /* RWCVF */
#define NV_XVE_PRIV_MISC_CYA_GPU_DL_UP_INIT                      0x00000000 /* RWC-V */
#define NV_XVE_PRIV_MISC_CYA_GPU_DL_UP_RESET                     0x00000001 /* RW--V */
#define NV_XVE_PRIV_MISC_CYA_GPU_DL_UP_NORESET                   0x00000000 /* RW--V */
#define NV_XVE_PRIV_MISC_CYA_GPU_HOT_RESET                            27:27 /* RWCVF */
#define NV_XVE_PRIV_MISC_CYA_GPU_HOT_RESET_INIT                  0x00000001 /* RWC-V */
#define NV_XVE_PRIV_MISC_CYA_GPU_HOT_RESET_RESET                 0x00000001 /* RW--V */
#define NV_XVE_PRIV_MISC_CYA_GPU_HOT_RESET_NORESET               0x00000000 /* RW--V */
#define NV_XVE_PRIV_MISC_RSVD_CYA_GPIO_D3HOT_POLARITY                 28:28 /* C--VF */
#define NV_XVE_PRIV_MISC_RSVD_CYA_GPIO_D3HOT_POLARITY_INIT       0x00000000 /* C---V */
#define NV_XVE_PRIV_MISC_RSVD_CYA_GPIO_D3HOT_IGNORE                   29:29 /* C--VF */
#define NV_XVE_PRIV_MISC_RSVD_CYA_GPIO_D3HOT_IGNORE_INIT         0x00000000 /* C---V */
#define NV_XVE_PRIV_MISC_RSVD_CYA_GPIO_XP_ENTER_L1                    30:30 /* C--VF */
#define NV_XVE_PRIV_MISC_RSVD_CYA_GPIO_XP_ENTER_L1_INIT          0x00000000 /* C---V */
#define NV_XVE_PRIV_MISC_CYA_PMCSR_POWER_STATE_D3HOT_IGNORE           31:31 /* RWCVF */
#define NV_XVE_PRIV_MISC_CYA_PMCSR_POWER_STATE_D3HOT_IGNORE_INIT 0x00000000 /* RWC-V */
#define NV_XVE_PRIV_XV_0                                               0x00000150 /* RW-4R */
#define NV_XVE_PRIV_XV_0_PM_PCIE_UTIL_MODE                                    2:0 /* RWCVF */
#define NV_XVE_PRIV_XV_0_PM_PCIE_UTIL_MODE_INIT                        0x00000005 /* RWC-V */
#define NV_XVE_PRIV_XV_0_UNUSED                                               3:3 /* RWCVF */
#define NV_XVE_PRIV_XV_0_UNUSED_INIT                                   0x00000000 /* RWC-V */
#define NV_XVE_PRIV_XV_0_CYA_CPU_REQUEST_RELAXED_ORDERING                     4:4 /* RWCVF */
#define NV_XVE_PRIV_XV_0_CYA_CPU_REQUEST_RELAXED_ORDERING_INIT         0x00000001 /* RWC-V */
#define NV_XVE_PRIV_XV_0_CYA_USE_SERR_ENABLE_FOR_ERROR_REPORTING              6:6 /* RWCVF */
#define NV_XVE_PRIV_XV_0_CYA_USE_SERR_ENABLE_FOR_ERROR_REPORTING_INIT  0x00000000 /* RWC-V */
#define NV_XVE_PRIV_XV_0_CYA_L0S_ENABLE                                       7:7 /* RWCVF */
#define NV_XVE_PRIV_XV_0_CYA_L0S_ENABLE_INIT                           0x00000001 /* RWC-V */
#define NV_XVE_PRIV_XV_0_CYA_L0S_ENABLE_ENABLED                        0x00000000 /* RW--V */
#define NV_XVE_PRIV_XV_0_CYA_L0S_ENABLE_DISABLED                       0x00000001 /* RW--V */
#define NV_XVE_PRIV_XV_0_CYA_L1_ENABLE                                        8:8 /* RWCVF */
#define NV_XVE_PRIV_XV_0_CYA_L1_ENABLE_INIT                            0x00000001 /* RWC-V */
#define NV_XVE_PRIV_XV_0_CYA_L1_ENABLE_ENABLED                         0x00000000 /* RW--V */
#define NV_XVE_PRIV_XV_0_CYA_L1_ENABLE_DISABLED                        0x00000001 /* RW--V */
#define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_NP_16BYTES                            9:9 /* C--VF */
#define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_NP_16BYTES_INIT                0x00000000 /* C---V */
#define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_NP_32BYTES                          10:10 /* C--VF */
#define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_NP_32BYTES_INIT                0x00000000 /* C---V */
#define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_NP_64BYTES                          11:11 /* C--VF */
#define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_NP_64BYTES_INIT                0x00000000 /* C---V */
#define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_PW_16BYTES                          12:12 /* C--VF */
#define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_PW_16BYTES_INIT                0x00000000 /* C---V */
#define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_PW_32BYTES                          13:13 /* C--VF */
#define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_PW_32BYTES_INIT                0x00000000 /* C---V */
#define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_PW_64BYTES                          14:14 /* C--VF */
#define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_PW_64BYTES_INIT                0x00000000 /* C---V */
#define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_NP_128BYTES                         15:15 /* C--VF */
#define NV_XVE_PRIV_XV_0_RSVD_CYA_MERGE_NP_128BYTES_INIT               0x00000000 /* C---V */
#define NV_XVE_PRIV_XV_0_RSVD_MERGER_HOLD_OFF_TIMER                         23:16 /* C--VF */
#define NV_XVE_PRIV_XV_0_RSVD_MERGER_HOLD_OFF_TIMER_INIT               0x00000000 /* C---V */
#define NV_XVE_PRIV_XV_0_CYA_CPLD_TO_L1                                     24:24 /* RWCVF */
#define NV_XVE_PRIV_XV_0_CYA_CPLD_TO_L1_INIT                           0x00000000 /* RWC-V */
#define NV_XVE_PRIV_XV_0_CYA_FORCE_SNOOP_WRITES_VC0                         25:25 /* RWCVF */
#define NV_XVE_PRIV_XV_0_CYA_FORCE_SNOOP_WRITES_VC0_INIT               0x00000000 /* RWC-V */
#define NV_XVE_PRIV_XV_0_CYA_FORCE_SNOOP_READS_VC0                          26:26 /* RWCVF */
#define NV_XVE_PRIV_XV_0_CYA_FORCE_SNOOP_READS_VC0_INIT                0x00000000 /* RWC-V */
#define NV_XVE_PRIV_XV_0_CYA_CFG_DL_UP                                      29:29 /* RWCVF */
#define NV_XVE_PRIV_XV_0_CYA_CFG_DL_UP_INIT                            0x00000001 /* RWC-V */
#define NV_XVE_PRIV_XV_0_CYA_CFG_DL_UP_RESET                           0x00000001 /* RW--V */
#define NV_XVE_PRIV_XV_0_CYA_CFG_DL_UP_NORESET                         0x00000000 /* RW--V */
#define NV_XVE_PRIV_XV_0_CYA_CFG_HOT_RESET                                  30:30 /* RWCVF */
#define NV_XVE_PRIV_XV_0_CYA_CFG_HOT_RESET_INIT                        0x00000001 /* RWC-V */
#define NV_XVE_PRIV_XV_0_CYA_CFG_HOT_RESET_RESET                       0x00000001 /* RW--V */
#define NV_XVE_PRIV_XV_0_CYA_CFG_HOT_RESET_NORESET                     0x00000000 /* RW--V */
#define NV_XVE_PRIV_XV_0_CYA_D3HOT_NO_SOFT_RESET                            31:31 /* RWCVF */
#define NV_XVE_PRIV_XV_0_CYA_D3HOT_NO_SOFT_RESET_DISABLE               0x00000000 /* RW--V */
#define NV_XVE_PRIV_XV_0_CYA_D3HOT_NO_SOFT_RESET_ENABLE                0x00000001 /* RWC-V */
#define NV_XVE_LTR_1                                                          0x00000254 /* RW-4R */
#define NV_XVE_LTR_1_SNOOP_LATENCY_VALUE                                             9:0 /* RWIVF */
#define NV_XVE_LTR_1_SNOOP_LATENCY_VALUE_INIT                                 0x00000000 /* RWI-V */
#define NV_XVE_LTR_1_SNOOP_LATENCY_SCALE                                           12:10 /* RWIVF */
#define NV_XVE_LTR_1_SNOOP_LATENCY_SCALE_INIT                                 0x00000000 /* RWI-V */
#define NV_XVE_LTR_1_NO_SNOOP_LATENCY_VALUE                                        25:16 /* RWIVF */
#define NV_XVE_LTR_1_NO_SNOOP_LATENCY_VALUE_INIT                              0x00000000 /* RWI-V */
#define NV_XVE_LTR_1_NO_SNOOP_LATENCY_SCALE                               28:26 /* RWIVF */
#define NV_XVE_LTR_1_NO_SNOOP_LATENCY_SCALE_INIT                              0x00000000 /* RWI-V */
#define NV_XVE_L1_PM_SUBSTATES_CTRL1                                 0x00000260 /* RW-4R */
#define NV_XVE_L1_PM_SUBSTATES_CTRL1_PCIPM_L1_2_EN                          0:0 /* RWIVF */
#define NV_XVE_L1_PM_SUBSTATES_CTRL1_PCIPM_L1_2_EN_INIT              0x00000000 /* RWI-V */
#define NV_XVE_L1_PM_SUBSTATES_CTRL1_PCIPM_L1_1_EN                          1:1 /* RWIVF */
#define NV_XVE_L1_PM_SUBSTATES_CTRL1_PCIPM_L1_1_EN_INIT              0x00000000 /* RWI-V */
#define NV_XVE_L1_PM_SUBSTATES_CTRL1_ASPM_L1_2_EN                           2:2 /* RWIVF */
#define NV_XVE_L1_PM_SUBSTATES_CTRL1_ASPM_L1_2_EN_INIT               0x00000000 /* RWI-V */
#define NV_XVE_L1_PM_SUBSTATES_CTRL1_ASPM_L1_1_EN                           3:3 /* RWIVF */
#define NV_XVE_L1_PM_SUBSTATES_CTRL1_ASPM_L1_1_EN_INIT               0x00000000 /* RWI-V */
#define NV_XVE_L1_PM_SUBSTATES_CTRL1_LTR_L1_2_THRES_VAL                   25:16 /* RWIVF */
#define NV_XVE_L1_PM_SUBSTATES_CTRL1_LTR_L1_2_THRES_VAL_INIT         0x00000000 /* RWI-V */
#define NV_XVE_L1_PM_SUBSTATES_CTRL1_LTR_L1_2_THRES_SCALE                 31:29 /* RWIVF */
#define NV_XVE_L1_PM_SUBSTATES_CTRL1_LTR_L1_2_THRES_SCALE_INIT       0x00000000 /* RWI-V */
#define NV_XVE_ROM_SHADOW_OFFSET                       0x00000418 /* RW-4R */
#define NV_XVE_ROM_SHADOW_OFFSET_VALUE                      19:12 /* RWIVF */
#define NV_XVE_ROM_SHADOW_OFFSET_VALUE_INIT            0x00000000 /* RWI-V */
#define NV_XVE_PRIV_MISC_1                                                    0x0000041C /* RW-4R */
#define NV_XVE_PRIV_MISC_1_NUM_NPT_VC1                                               7:0 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_NUM_NPT_VC1_INIT                                   0x00000000 /* RWC-V */
#define NV_XVE_PRIV_MISC_1_CYA_AER                                                   8:8 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_CYA_AER_ENABLE                                     0x00000001 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_AER_DISABLE                                    0x00000000 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_AER_INIT                                       0x00000001 /* RWC-V */
#define NV_XVE_PRIV_MISC_1_CYA_VEND_SPECIFIC_ENHANCED_CAP                          10:10 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_CYA_VEND_SPECIFIC_ENHANCED_CAP_ENABLE              0x00000001 /* RWC-V */
#define NV_XVE_PRIV_MISC_1_CYA_VEND_SPECIFIC_ENHANCED_CAP_DISABLE             0x00000000 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_GEN2_PROTO_OVERRIDE_EN                              11:11 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_CYA_GEN2_PROTO_OVERRIDE_EN_DISABLED                0x00000000 /* RWC-V */
#define NV_XVE_PRIV_MISC_1_CYA_GEN2_PROTO_OVERRIDE_EN_ENABLED                 0x00000001 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_GEN2_PROTO_OVERRIDE_VAL                             12:12 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_CYA_GEN2_PROTO_OVERRIDE_VAL_GEN1P1                 0x00000001 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_GEN2_PROTO_OVERRIDE_VAL_GEN2                   0x00000000 /* RWC-V */
#define NV_XVE_PRIV_MISC_1_CYA_GEN2_SPEED_OVERRIDE_EN                              13:13 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_CYA_GEN2_SPEED_OVERRIDE_EN_DISABLED                0x00000000 /* RWC-V */
#define NV_XVE_PRIV_MISC_1_CYA_GEN2_SPEED_OVERRIDE_EN_ENABLED                 0x00000001 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_GEN2_SPEED_OVERRIDE_VAL                             14:14 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_CYA_GEN2_SPEED_OVERRIDE_VAL_2P5                    0x00000001 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_GEN2_SPEED_OVERRIDE_VAL_5P0                    0x00000000 /* RWC-V */
#define NV_XVE_PRIV_MISC_1_CYA_GEN3_PROTO_OVERRIDE_EN                              15:15 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_CYA_GEN3_PROTO_OVERRIDE_EN_DISABLED                0x00000000 /* RWC-V */
#define NV_XVE_PRIV_MISC_1_CYA_GEN3_PROTO_OVERRIDE_EN_ENABLED                 0x00000001 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_GEN3_PROTO_OVERRIDE_VAL                             16:16 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_CYA_GEN3_PROTO_OVERRIDE_VAL_GEN2                   0x00000001 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_GEN3_PROTO_OVERRIDE_VAL_GEN3                   0x00000000 /* RWC-V */
#define NV_XVE_PRIV_MISC_1_CYA_MSGBOX                                              17:17 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_CYA_MSGBOX_ENABLE                                  0x00000001 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_MSGBOX_DISABLE                                 0x00000000 /* RWC-V */
#define NV_XVE_PRIV_MISC_1_CYA_LINKCAP_CLOCK_PM                                    18:18 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_CYA_LINKCAP_CLOCK_PM_DISABLE                       0x00000000 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_LINKCAP_CLOCK_PM_ENABLE                        0x00000001 /* RWC-V */
#define NV_XVE_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY                        21:19 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_INIT              0x00000006 /* RWC-V */
#define NV_XVE_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_0                 0x00000000 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_1                 0x00000001 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_2                 0x00000002 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_3                 0x00000003 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_4                 0x00000004 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_5                 0x00000005 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_6                 0x00000006 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_DEVCAP_L1_ACCEPTABLE_LATENCY_7                 0x00000007 /* RW--V */
#define NV_XVE_PRIV_MISC_1_RSVD_CYA_NO_P2P_WRT_BUBBLE                              22:22 /* C--VF */
#define NV_XVE_PRIV_MISC_1_RSVD_CYA_NO_P2P_WRT_BUBBLE_DISABLE                 0x00000000 /* C---V */
#define NV_XVE_PRIV_MISC_1_CYA_ROUTE_MSGBOX_CMD_INTR_TO_PMU                        23:23 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_CYA_ROUTE_MSGBOX_CMD_INTR_TO_PMU_ENABLE            0x00000001 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_ROUTE_MSGBOX_CMD_INTR_TO_PMU_DISABLE           0x00000000 /* RWC-V */
#define NV_XVE_PRIV_MISC_1_CYA_SHADOW_RCB                                          24:24 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_CYA_SHADOW_RCB_64B                                 0x00000000 /* RWC-V */
#define NV_XVE_PRIV_MISC_1_CYA_SHADOW_RCB_128B                                0x00000001 /* RW--V */
#define NV_XVE_PRIV_MISC_1_RSVD_CYA_WR_BLOCK_CPL_ONLY_WHEN_P2P_CPL                 25:25 /* C--VF */
#define NV_XVE_PRIV_MISC_1_RSVD_CYA_WR_BLOCK_CPL_ONLY_WHEN_P2P_CPL_DISABLE    0x00000000 /* C---V */
#define NV_XVE_PRIV_MISC_1_CYA_SLOT_CLK_CFG_OVERRIDE_EN                            26:26 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_CYA_SLOT_CLK_CFG_OVERRIDE_EN_DISABLED              0x00000000 /* RWC-V */
#define NV_XVE_PRIV_MISC_1_CYA_SLOT_CLK_CFG_OVERRIDE_EN_ENABLED               0x00000001 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_SLOT_CLK_CFG_OVERRIDE_VAL                           27:27 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_CYA_SLOT_CLK_CFG_OVERRIDE_VAL_ENABLE               0x00000001 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_SLOT_CLK_CFG_OVERRIDE_VAL_DISABLE              0x00000000 /* RWC-V */
#define NV_XVE_PRIV_MISC_1_CYA_WRITES_RELAXED_ORDERING                             28:28 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_CYA_WRITES_RELAXED_ORDERING_ENABLE                 0x00000001 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_WRITES_RELAXED_ORDERING_DISABLE                0x00000000 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_WRITES_RELAXED_ORDERING_INIT                   0x00000000 /* RWC-V */
#define NV_XVE_PRIV_MISC_1_CYA_GEN3_SPEED_OVERRIDE_EN                              30:30 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_CYA_GEN3_SPEED_OVERRIDE_EN_DISABLED                0x00000000 /* RWC-V */
#define NV_XVE_PRIV_MISC_1_CYA_GEN3_SPEED_OVERRIDE_EN_ENABLED                 0x00000001 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_GEN3_SPEED_OVERRIDE_VAL                             31:31 /* RWCVF */
#define NV_XVE_PRIV_MISC_1_CYA_GEN3_SPEED_OVERRIDE_VAL_5P0                    0x00000001 /* RW--V */
#define NV_XVE_PRIV_MISC_1_CYA_GEN3_SPEED_OVERRIDE_VAL_8P0                    0x00000000 /* RWC-V */
#define NV_XVE_AER_UNCORR_ERR                                    0x00000424 /* RWC4R */
#define NV_XVE_AER_UNCORR_ERR_RSVD                                      0:0 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_RSVD_INIT                          0x00000000 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_DLINK_PROTO_ERR                           4:4 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_DLINK_PROTO_ERR_ACTIVE             0x00000001 /* R---V */
#define NV_XVE_AER_UNCORR_ERR_DLINK_PROTO_ERR_NOT_ACTIVE         0x00000000 /* R-C-V */
#define NV_XVE_AER_UNCORR_ERR_DLINK_PROTO_ERR_CLEAR              0x00000001 /* -W--C */
#define NV_XVE_AER_UNCORR_ERR_SURPRISE_DOWN                             5:5 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_SURPRISE_DOWN_INIT                 0x00000000 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_POISONED_TLP                            12:12 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_POISONED_TLP_ACTIVE                0x00000001 /* R---V */
#define NV_XVE_AER_UNCORR_ERR_POISONED_TLP_NOT_ACTIVE            0x00000000 /* R-C-V */
#define NV_XVE_AER_UNCORR_ERR_POISONED_TLP_CLEAR                 0x00000001 /* -W--C */
#define NV_XVE_AER_UNCORR_ERR_FC_PROTO_ERR                            13:13 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_FC_PROTO_ERR_ACTIVE                0x00000001 /* R---V */
#define NV_XVE_AER_UNCORR_ERR_FC_PROTO_ERR_NOT_ACTIVE            0x00000000 /* R-C-V */
#define NV_XVE_AER_UNCORR_ERR_FC_PROTO_ERR_CLEAR                 0x00000001 /* -W--C */
#define NV_XVE_AER_UNCORR_ERR_CPL_TIMEOUT                             14:14 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_CPL_TIMEOUT_ACTIVE                 0x00000001 /* R---V */
#define NV_XVE_AER_UNCORR_ERR_CPL_TIMEOUT_NOT_ACTIVE             0x00000000 /* R-C-V */
#define NV_XVE_AER_UNCORR_ERR_CPL_TIMEOUT_CLEAR                  0x00000001 /* -W--C */
#define NV_XVE_AER_UNCORR_ERR_CPL_ABORT                               15:15 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_CPL_ABORT_ACTIVE                   0x00000001 /* R---V */
#define NV_XVE_AER_UNCORR_ERR_CPL_ABORT_NOT_ACTIVE               0x00000000 /* R-C-V */
#define NV_XVE_AER_UNCORR_ERR_CPL_ABORT_CLEAR                    0x00000001 /* -W--C */
#define NV_XVE_AER_UNCORR_ERR_UNEXP_CPL                               16:16 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_UNEXP_CPL_ACTIVE                   0x00000001 /* R---V */
#define NV_XVE_AER_UNCORR_ERR_UNEXP_CPL_NOT_ACTIVE               0x00000000 /* R-C-V */
#define NV_XVE_AER_UNCORR_ERR_UNEXP_CPL_CLEAR                    0x00000001 /* -W--C */
#define NV_XVE_AER_UNCORR_ERR_RCVR_OVERFLOW                           17:17 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_RCVR_OVERFLOW_ACTIVE               0x00000001 /* R---V */
#define NV_XVE_AER_UNCORR_ERR_RCVR_OVERFLOW_NOT_ACTIVE           0x00000000 /* R-C-V */
#define NV_XVE_AER_UNCORR_ERR_RCVR_OVERFLOW_CLEAR                0x00000001 /* -W--C */
#define NV_XVE_AER_UNCORR_ERR_MALFORMED_TLP                           18:18 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_MALFORMED_TLP_ACTIVE               0x00000001 /* R---V */
#define NV_XVE_AER_UNCORR_ERR_MALFORMED_TLP_NOT_ACTIVE           0x00000000 /* R-C-V */
#define NV_XVE_AER_UNCORR_ERR_MALFORMED_TLP_CLEAR                0x00000001 /* -W--C */
#define NV_XVE_AER_UNCORR_ERR_ECRC_ERROR                              19:19 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_ECRC_ERROR_INIT                    0x00000000 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_UNSUPPORTED_REQ                         20:20 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_UNSUPPORTED_REQ_ACTIVE             0x00000001 /* R---V */
#define NV_XVE_AER_UNCORR_ERR_UNSUPPORTED_REQ_NOT_ACTIVE         0x00000000 /* R-C-V */
#define NV_XVE_AER_UNCORR_ERR_UNSUPPORTED_REQ_CLEAR              0x00000001 /* -W--C */
#define NV_XVE_AER_UNCORR_ERR_ACS_VIOLATION                           21:21 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_ACS_VIOLATION_INIT                 0x00000000 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_INTERNAL_ERROR                          22:22 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_INTERNAL_ERROR_INIT                0x00000000 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_MC_BLOCKED_TLP                          23:23 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_MC_BLOCKED_TLP_INIT                0x00000000 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_ATOMIC_OP_EGRESS_BLOCKED                24:24 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_ATOMIC_OP_EGRESS_BLOCKED_INIT      0x00000000 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_TLP_PREFIX_BLOCKED                      25:25 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_TLP_PREFIX_BLOCKED_INIT            0x00000000 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_MASK                               0x00000428 /* RW-4R */
#define NV_XVE_AER_UNCORR_ERR_MASK_RSVD                                 0:0 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_MASK_RSVD_INIT                     0x00000000 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_MASK_DLINK_PROTO_ERR                      4:4 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_MASK_DLINK_PROTO_ERR_NOT_MASKED    0x00000000 /* RWC-V */
#define NV_XVE_AER_UNCORR_ERR_MASK_DLINK_PROTO_ERR_MASKED        0x00000001 /* RW--V */
#define NV_XVE_AER_UNCORR_ERR_MASK_SURPRISE_DOWN                        5:5 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_MASK_SURPRISE_DOWN_INIT            0x00000000 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_MASK_POISONED_TLP                       12:12 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_MASK_POISONED_TLP_NOT_MASKED       0x00000000 /* RWC-V */
#define NV_XVE_AER_UNCORR_ERR_MASK_POISONED_TLP_MASKED           0x00000001 /* RW--V */
#define NV_XVE_AER_UNCORR_ERR_MASK_FC_PROTO_ERR                       13:13 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_MASK_FC_PROTO_ERR_NOT_MASKED       0x00000000 /* RWC-V */
#define NV_XVE_AER_UNCORR_ERR_MASK_FC_PROTO_ERR_MASKED           0x00000001 /* RW--V */
#define NV_XVE_AER_UNCORR_ERR_MASK_CPL_TIMEOUT                        14:14 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_MASK_CPL_TIMEOUT_NOT_MASKED        0x00000000 /* RWC-V */
#define NV_XVE_AER_UNCORR_ERR_MASK_CPL_TIMEOUT_MASKED            0x00000001 /* RW--V */
#define NV_XVE_AER_UNCORR_ERR_MASK_CPL_ABORT                          15:15 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_MASK_CPL_ABORT_NOT_MASKED          0x00000000 /* RWC-V */
#define NV_XVE_AER_UNCORR_ERR_MASK_CPL_ABORT_MASKED              0x00000001 /* RW--V */
#define NV_XVE_AER_UNCORR_ERR_MASK_UNEXP_CPL                          16:16 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_MASK_UNEXP_CPL_NOT_MASKED          0x00000000 /* RWC-V */
#define NV_XVE_AER_UNCORR_ERR_MASK_UNEXP_CPL_MASKED              0x00000001 /* RW--V */
#define NV_XVE_AER_UNCORR_ERR_MASK_RCVR_OVERFLOW                      17:17 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_MASK_RCVR_OVERFLOW_NOT_MASKED      0x00000000 /* RWC-V */
#define NV_XVE_AER_UNCORR_ERR_MASK_RCVR_OVERFLOW_MASKED          0x00000001 /* RW--V */
#define NV_XVE_AER_UNCORR_ERR_MASK_MALFORMED_TLP                      18:18 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_MASK_MALFORMED_TLP_NOT_MASKED      0x00000000 /* RWC-V */
#define NV_XVE_AER_UNCORR_ERR_MASK_MALFORMED_TLP_MASKED          0x00000001 /* RW--V */
#define NV_XVE_AER_UNCORR_ERR_MASK_ECRC_ERR                           19:19 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_MASK_ECRC_ERR_INIT                 0x00000000 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_MASK_UNSUPPORTED_REQ                    20:20 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_MASK_UNSUPPORTED_REQ_NOT_MASKED    0x00000000 /* RWC-V */
#define NV_XVE_AER_UNCORR_ERR_MASK_UNSUPPORTED_REQ_MASKED        0x00000001 /* RW--V */
#define NV_XVE_AER_UNCORR_ERR_MASK_ACS_VIOLATION                      21:21 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_MASK_ACS_VIOLATION_INIT            0x00000000 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_MASK_INTERNAL_ERROR                     22:22 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_MASK_INTERNAL_ERROR_INIT           0x00000000 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_MASK_MC_BLOCKED_TLP                     23:23 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_MASK_MC_BLOCKED_TLP_INIT           0x00000000 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_MASK_ATOMIC_OP_EGRESS_BLOCKED           24:24 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_MASK_ATOMIC_OP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_MASK_TLP_PREFIX_BLOCKED                 25:25 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_MASK_TLP_PREFIX_BLOCKED_INIT       0x00000000 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_SEVR                               0x0000042C /* RW-4R */
#define NV_XVE_AER_UNCORR_ERR_SEVR_RSVD                                 0:0 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_SEVR_RSVD_INIT                     0x00000000 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_DLINK_PROTO_ERR                      4:4 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_SEVR_DLINK_PROTO_ERR_NON_FATAL     0x00000000 /* RW--V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_DLINK_PROTO_ERR_FATAL         0x00000001 /* RWC-V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_SURPRISE_DOWN                        5:5 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_SEVR_SURPRISE_DOWN_INIT            0x00000001 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_POISONED_TLP                       12:12 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_SEVR_POISONED_TLP_NON_FATAL        0x00000000 /* RWC-V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_POISONED_TLP_FATAL            0x00000001 /* RW--V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_FC_PROTO_ERR                       13:13 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_SEVR_FC_PROTO_ERR_NON_FATAL        0x00000000 /* RW--V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_FC_PROTO_ERR_FATAL            0x00000001 /* RWC-V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_CPL_TIMEOUT                        14:14 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_SEVR_CPL_TIMEOUT_NON_FATAL         0x00000000 /* RWC-V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_CPL_TIMEOUT_FATAL             0x00000001 /* RW--V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_CPL_ABORT                          15:15 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_SEVR_CPL_ABORT_NON_FATAL           0x00000000 /* RWC-V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_CPL_ABORT_FATAL               0x00000001 /* RW--V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_UNEXP_CPL                          16:16 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_SEVR_UNEXP_CPL_NON_FATAL           0x00000000 /* RWC-V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_UNEXP_CPL_FATAL               0x00000001 /* RW--V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_RCVR_OVERFLOW                      17:17 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_SEVR_RCVR_OVERFLOW_NON_FATAL       0x00000000 /* RW--V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_RCVR_OVERFLOW_FATAL           0x00000001 /* RWC-V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_MALFORMED_TLP                      18:18 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_SEVR_MALFORMED_TLP_NON_FATAL       0x00000000 /* RW--V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_MALFORMED_TLP_FATAL           0x00000001 /* RWC-V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_ECRC_ERR                           19:19 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_SEVR_ECRC_ERR_INIT                 0x00000000 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_UNSUPPORTED_REQ                    20:20 /* RWCVF */
#define NV_XVE_AER_UNCORR_ERR_SEVR_UNSUPPORTED_REQ_NON_FATAL     0x00000000 /* RWC-V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_UNSUPPORTED_REQ_FATAL         0x00000001 /* RW--V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_ACS_VIOLATION                      21:21 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_SEVR_ACS_VIOLATION_INIT            0x00000000 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_INTERNAL_ERROR                     22:22 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_SEVR_INTERNAL_ERROR_INIT           0x00000001 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_MC_BLOCKED_TLP                     23:23 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_SEVR_MC_BLOCKED_TLP_INIT           0x00000000 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_ATOMIC_OP_EGRESS_BLOCKED           24:24 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_SEVR_ATOMIC_OP_EGRESS_BLOCKED_INIT 0x00000000 /* C---V */
#define NV_XVE_AER_UNCORR_ERR_SEVR_TLP_PREFIX_BLOCKED                 25:25 /* C--VF */
#define NV_XVE_AER_UNCORR_ERR_SEVR_TLP_PREFIX_BLOCKED_INIT       0x00000000 /* C---V */
#define NV_XVE_AER_CORR_ERR                                      0x00000430 /* RW-4R */
#define NV_XVE_AER_CORR_ERR_RCV_ERR                                     0:0 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_RCV_ERR_NOT_ACTIVE                   0x00000000 /* R-C-V */
#define NV_XVE_AER_CORR_ERR_RCV_ERR_ACTIVE                       0x00000001 /* R---V */
#define NV_XVE_AER_CORR_ERR_RCV_ERR_CLEAR                        0x00000001 /* -W--C */
#define NV_XVE_AER_CORR_ERR_BAD_TLP                                     6:6 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_BAD_TLP_NOT_ACTIVE                   0x00000000 /* R-C-V */
#define NV_XVE_AER_CORR_ERR_BAD_TLP_ACTIVE                       0x00000001 /* R---V */
#define NV_XVE_AER_CORR_ERR_BAD_TLP_CLEAR                        0x00000001 /* -W--C */
#define NV_XVE_AER_CORR_ERR_BAD_DLLP                                    7:7 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_BAD_DLLP_NOT_ACTIVE                  0x00000000 /* R-C-V */
#define NV_XVE_AER_CORR_ERR_BAD_DLLP_ACTIVE                      0x00000001 /* R---V */
#define NV_XVE_AER_CORR_ERR_BAD_DLLP_CLEAR                       0x00000001 /* -W--C */
#define NV_XVE_AER_CORR_ERR_RPLY_ROLLOVER                               8:8 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_RPLY_ROLLOVER_NOT_ACTIVE             0x00000000 /* R-C-V */
#define NV_XVE_AER_CORR_ERR_RPLY_ROLLOVER_ACTIVE                 0x00000001 /* R---V */
#define NV_XVE_AER_CORR_ERR_RPLY_ROLLOVER_CLEAR                  0x00000001 /* -W--C */
#define NV_XVE_AER_CORR_ERR_RPLY_TIMEOUT                              12:12 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_RPLY_TIMEOUT_NOT_ACTIVE              0x00000000 /* R-C-V */
#define NV_XVE_AER_CORR_ERR_RPLY_TIMEOUT_ACTIVE                  0x00000001 /* R---V */
#define NV_XVE_AER_CORR_ERR_RPLY_TIMEOUT_CLEAR                   0x00000001 /* -W--C */
#define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL                         13:13 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL_NOT_ACTIVE         0x00000000 /* R-C-V */
#define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL_ACTIVE             0x00000001 /* R---V */
#define NV_XVE_AER_CORR_ERR_ADVISORY_NONFATAL_CLEAR              0x00000001 /* -W--C */
#define NV_XVE_AER_CORR_ERR_INTERNAL_ERROR                            14:14 /* C--VF */
#define NV_XVE_AER_CORR_ERR_INTERNAL_ERROR_INIT                  0x00000000 /* C---V */
#define NV_XVE_AER_CORR_ERR_HEADER_LOG_OVERFLOW                       15:15 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_HEADER_LOG_OVERFLOW_NOT_ACTIVE       0x00000000 /* R-C-V */
#define NV_XVE_AER_CORR_ERR_HEADER_LOG_OVERFLOW_ACTIVE           0x00000001 /* R---V */
#define NV_XVE_AER_CORR_ERR_HEADER_LOG_OVERFLOW_CLEAR            0x00000001 /* -W--C */
#define NV_XVE_AER_CORR_ERR_MASK                                 0x00000434 /* RW-4R */
#define NV_XVE_AER_CORR_ERR_MASK_RCV_ERR                                0:0 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_MASK_RCV_ERR_NOT_MASKED              0x00000000 /* RWC-V */
#define NV_XVE_AER_CORR_ERR_MASK_RCV_ERR_MASKED                  0x00000001 /* RW--V */
#define NV_XVE_AER_CORR_ERR_MASK_BAD_TLP                                6:6 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_MASK_BAD_TLP_NOT_MASKED              0x00000000 /* RWC-V */
#define NV_XVE_AER_CORR_ERR_MASK_BAD_TLP_MASKED                  0x00000001 /* RW--V */
#define NV_XVE_AER_CORR_ERR_MASK_BAD_DLLP                               7:7 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_MASK_BAD_DLLP_NOT_MASKED             0x00000000 /* RWC-V */
#define NV_XVE_AER_CORR_ERR_MASK_BAD_DLLP_MASKED                 0x00000001 /* RW--V */
#define NV_XVE_AER_CORR_ERR_MASK_RPLY_ROLLOVER                          8:8 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_MASK_RPLY_ROLLOVER_NOT_MASKED        0x00000000 /* RWC-V */
#define NV_XVE_AER_CORR_ERR_MASK_RPLY_ROLLOVER_MASKED            0x00000001 /* RW--V */
#define NV_XVE_AER_CORR_ERR_MASK_RPLY_TIMEOUT                         12:12 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_MASK_RPLY_TIMEOUT_NOT_MASKED         0x00000000 /* RWC-V */
#define NV_XVE_AER_CORR_ERR_MASK_RPLY_TIMEOUT_MASKED             0x00000001 /* RW--V */
#define NV_XVE_AER_CORR_ERR_MASK_ADVISORY_NONFATAL                    13:13 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_MASK_ADVISORY_NONFATAL_NOT_MASKED    0x00000000 /* RW--V */
#define NV_XVE_AER_CORR_ERR_MASK_ADVISORY_NONFATAL_MASKED        0x00000001 /* RWC-V */
#define NV_XVE_AER_CORR_ERR_MASK_INTERNAL_ERROR                       14:14 /* C--VF */
#define NV_XVE_AER_CORR_ERR_MASK_INTERNAL_ERROR_INIT             0x00000000 /* C---V */
#define NV_XVE_AER_CORR_ERR_MASK_HEADER_LOG_OVERFLOW                  15:15 /* RWCVF */
#define NV_XVE_AER_CORR_ERR_MASK_HEADER_LOG_OVERFLOW_NOT_MASKED  0x00000000 /* RW--V */
#define NV_XVE_AER_CORR_ERR_MASK_HEADER_LOG_OVERFLOW_MASKED      0x00000001 /* RWC-V */
#define NV_XVE_PRIV_INTR                               0x00000480 /* RW-4R */
#define NV_XVE_PRIV_INTR_CPL_TIMEOUT                          0:0 /* RWIVF */
#define NV_XVE_PRIV_INTR_CPL_TIMEOUT_NOT_PENDING           0x00000000 /* R-I-V */
#define NV_XVE_PRIV_INTR_CPL_TIMEOUT_PENDING               0x00000001 /* R---V */
#define NV_XVE_PRIV_INTR_CPL_TIMEOUT_RESET                     0x00000001 /* -W--C */
#define NV_XVE_PRIV_INTR_MSGBOX_INTERRUPT                             1:1 /* RWIVF */
#define NV_XVE_PRIV_INTR_MSGBOX_INTERRUPT_NOT_PENDING          0x00000000 /* R-I-V */
#define NV_XVE_PRIV_INTR_MSGBOX_INTERRUPT_PENDING              0x00000001 /* R---V */
#define NV_XVE_PRIV_INTR_AZA_CPL_TIMEOUT                              2:2 /* RWIVF */
#define NV_XVE_PRIV_INTR_AZA_CPL_TIMEOUT_NOT_PENDING           0x00000000 /* R-I-V */
#define NV_XVE_PRIV_INTR_AZA_CPL_TIMEOUT_PENDING               0x00000001 /* R---V */
#define NV_XVE_PRIV_INTR_AZA_CPL_TIMEOUT_RESET                 0x00000001 /* -W--C */
#define NV_XVE_PRIV_INTR_P2PSLAVE_CPL_TIMEOUT                         3:3 /* RWIVF */
#define NV_XVE_PRIV_INTR_P2PSLAVE_CPL_TIMEOUT_NOT_PENDING      0x00000000 /* R-I-V */
#define NV_XVE_PRIV_INTR_P2PSLAVE_CPL_TIMEOUT_PENDING          0x00000001 /* R---V */
#define NV_XVE_PRIV_INTR_P2PSLAVE_CPL_TIMEOUT_RESET            0x00000001 /* -W--C */
#define NV_XVE_PRIV_INTR_POSTED_DEADLOCK_TIMEOUT                      4:4 /* RWIVF */
#define NV_XVE_PRIV_INTR_POSTED_DEADLOCK_TIMEOUT_NOT_PENDING   0x00000000 /* R-I-V */
#define NV_XVE_PRIV_INTR_POSTED_DEADLOCK_TIMEOUT_PENDING       0x00000001 /* R---V */
#define NV_XVE_PRIV_INTR_POSTED_DEADLOCK_TIMEOUT_RESET         0x00000001 /* -W--C */
#define NV_XVE_PRIV_INTR_BAR_OVERLAP                                  5:5 /* RWIVF */
#define NV_XVE_PRIV_INTR_BAR_OVERLAP_NOT_PENDING               0x00000000 /* R-I-V */
#define NV_XVE_PRIV_INTR_BAR_OVERLAP_PENDING                   0x00000001 /* R---V */
#define NV_XVE_PRIV_INTR_BAR_OVERLAP_RESET                     0x00000001 /* -W--C */
#define NV_XVE_PRIV_INTR_P2PMASTER_CPL_TIMEOUT                        8:8 /* RWIVF */
#define NV_XVE_PRIV_INTR_P2PMASTER_CPL_TIMEOUT_NOT_PENDING     0x00000000 /* R-I-V */
#define NV_XVE_PRIV_INTR_P2PMASTER_CPL_TIMEOUT_PENDING         0x00000001 /* R---V */
#define NV_XVE_PRIV_INTR_P2PMASTER_CPL_TIMEOUT_RESET           0x00000001 /* -W--C */
#define NV_XVE_PRIV_INTR_P2P_SPLIT_ERR                                9:9 /* RWIVF */
#define NV_XVE_PRIV_INTR_P2P_SPLIT_ERR_NOT_PENDING             0x00000000 /* R-I-V */
#define NV_XVE_PRIV_INTR_P2P_SPLIT_ERR_PENDING                 0x00000001 /* R---V */
#define NV_XVE_PRIV_INTR_P2P_SPLIT_ERR_RESET                   0x00000001 /* -W--C */
#define NV_XVE_PRIV_INTR_OBFF_MSG                                   10:10 /* RWIVF */
#define NV_XVE_PRIV_INTR_OBFF_MSG_NOT_PENDING                  0x00000000 /* R-I-V */
#define NV_XVE_PRIV_INTR_OBFF_MSG_PENDING                      0x00000001 /* R---V */
#define NV_XVE_PRIV_INTR_OBFF_MSG_RESET                        0x00000001 /* -W--C */
#define NV_XVE_PRIV_INTR_EN                                 0x00000484 /* RW-4R */
#define NV_XVE_PRIV_INTR_EN_CPL_TIMEOUT                        0:0 /* RWIVF */
#define NV_XVE_PRIV_INTR_EN_CPL_TIMEOUT_DISABLED             0x00000000 /* RWI-V */
#define NV_XVE_PRIV_INTR_EN_CPL_TIMEOUT_ENABLED                 0x00000001 /* RW--V */
#define NV_XVE_PRIV_INTR_EN_CPL_TIMEOUT__PROD                 0x00000001 /* RW--V */
#define NV_XVE_PRIV_INTR_EN_MSGBOX_INTERRUPT                            1:1 /* RWIVF */
#define NV_XVE_PRIV_INTR_EN_MSGBOX_INTERRUPT_DISABLED            0x00000000 /* RWI-V */
#define NV_XVE_PRIV_INTR_EN_MSGBOX_INTERRUPT_ENABLED             0x00000001 /* RW--V */
#define NV_XVE_PRIV_INTR_EN_AZA_CPL_TIMEOUT                             2:2 /* RWIVF */
#define NV_XVE_PRIV_INTR_EN_AZA_CPL_TIMEOUT_DISABLED             0x00000000 /* RWI-V */
#define NV_XVE_PRIV_INTR_EN_AZA_CPL_TIMEOUT_ENABLED              0x00000001 /* RW--V */
#define NV_XVE_PRIV_INTR_EN_P2PSLAVE_CPL_TIMEOUT                        3:3 /* RWIVF */
#define NV_XVE_PRIV_INTR_EN_P2PSLAVE_CPL_TIMEOUT_DISABLED        0x00000000 /* RWI-V */
#define NV_XVE_PRIV_INTR_EN_P2PSLAVE_CPL_TIMEOUT_ENABLED         0x00000001 /* RW--V */
#define NV_XVE_PRIV_INTR_EN_POSTED_DEADLOCK_TIMEOUT                     4:4 /* RWIVF */
#define NV_XVE_PRIV_INTR_EN_POSTED_DEADLOCK_TIMEOUT_DISABLED     0x00000000 /* RWI-V */
#define NV_XVE_PRIV_INTR_EN_POSTED_DEADLOCK_TIMEOUT_ENABLED      0x00000001 /* RW--V */
#define NV_XVE_PRIV_INTR_EN_BAR_OVERLAP                                 5:5 /* RWIVF */
#define NV_XVE_PRIV_INTR_EN_BAR_OVERLAP_DISABLED                 0x00000000 /* RWI-V */
#define NV_XVE_PRIV_INTR_EN_BAR_OVERLAP_ENABLED                  0x00000001 /* RW--V */
#define NV_XVE_PRIV_INTR_EN_P2PMASTER_CPL_TIMEOUT                       8:8 /* RWIVF */
#define NV_XVE_PRIV_INTR_EN_P2PMASTER_CPL_TIMEOUT_DISABLED       0x00000000 /* RWI-V */
#define NV_XVE_PRIV_INTR_EN_P2PMASTER_CPL_TIMEOUT_ENABLED        0x00000001 /* RW--V */
#define NV_XVE_PRIV_INTR_EN_P2P_SPLIT_ERR                               9:9 /* RWIVF */
#define NV_XVE_PRIV_INTR_EN_P2P_SPLIT_ERR_DISABLED               0x00000000 /* RWI-V */
#define NV_XVE_PRIV_INTR_EN_P2P_SPLIT_ERR_ENABLED                0x00000001 /* RW--V */
#define NV_XVE_PRIV_INTR_EN_OBFF_MSG                                  10:10 /* RWIVF */
#define NV_XVE_PRIV_INTR_EN_OBFF_MSG_DISABLED                    0x00000000 /* RWI-V */
#define NV_XVE_PRIV_INTR_EN_OBFF_MSG_ENABLED                     0x00000001 /* RW--V */
#define NV_XVE_ERROR_COUNTER                                     0x000004AC /* R--4R */
#define NV_XVE_ERROR_COUNTER_RSVD_CORR_ERROR_COUNT_VALUE                7:0 /* C--VF */
#define NV_XVE_ERROR_COUNTER_RSVD_CORR_ERROR_COUNT_VALUE_INIT    0x00000000 /* C---V */
#define NV_XVE_ERROR_COUNTER_NON_FATAL_ERROR_COUNT_VALUE               15:8 /* R-XVF */
#define NV_XVE_ERROR_COUNTER_FATAL_ERROR_COUNT_VALUE                  23:16 /* R-XVF */
#define NV_XVE_ERROR_COUNTER_UNSUPP_REQ_COUNT_VALUE                   31:24 /* R-XVF */
#define NV_XVE_ERROR_COUNTER_FREEZE                                    0x000004B0 /* RWC4R */
#define NV_XVE_ERROR_COUNTER_FREEZE_CORR_ERROR_COUNT                          0:0 /* RWCVF */
#define NV_XVE_ERROR_COUNTER_FREEZE_CORR_ERROR_COUNT_DISABLED          0x00000000 /* RWC-V */
#define NV_XVE_ERROR_COUNTER_FREEZE_CORR_ERROR_COUNT_ENABLED           0x00000001 /* RW--V */
#define NV_XVE_ERROR_COUNTER_FREEZE_NON_FATAL_ERROR_COUNT                     1:1 /* RWCVF */
#define NV_XVE_ERROR_COUNTER_FREEZE_NON_FATAL_ERROR_COUNT_DISABLED     0x00000000 /* RWC-V */
#define NV_XVE_ERROR_COUNTER_FREEZE_NON_FATAL_ERROR_COUNT_ENABLED      0x00000001 /* RW--V */
#define NV_XVE_ERROR_COUNTER_FREEZE_FATAL_ERROR_COUNT                         2:2 /* RWCVF */
#define NV_XVE_ERROR_COUNTER_FREEZE_FATAL_ERROR_COUNT_DISABLED         0x00000000 /* RWC-V */
#define NV_XVE_ERROR_COUNTER_FREEZE_FATAL_ERROR_COUNT_ENABLED          0x00000001 /* RW--V */
#define NV_XVE_ERROR_COUNTER_FREEZE_UNSUPP_REQ_COUNT                          3:3 /* RWCVF */
#define NV_XVE_ERROR_COUNTER_FREEZE_UNSUPP_REQ_COUNT_DISABLED          0x00000000 /* RWC-V */
#define NV_XVE_ERROR_COUNTER_FREEZE_UNSUPP_REQ_COUNT_ENABLED           0x00000001 /* RW--V */
#define NV_XVE_ERROR_COUNTER_RESET                                               0x000004B8 /* RWC4R */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_CHIPSET_XMIT_L0S_ENTRY_COUNT                    0:0 /* C--VF */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_CHIPSET_XMIT_L0S_ENTRY_COUNT_DONE        0x00000000 /* C---V */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_GPU_XMIT_L0S_ENTRY_COUNT                        1:1 /* C--VF */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_GPU_XMIT_L0S_ENTRY_COUNT_DONE            0x00000000 /* C---V */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_L1_ENTRY_COUNT                                  2:2 /* C--VF */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_L1_ENTRY_COUNT_DONE                      0x00000000 /* C---V */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_L1P_ENTRY_COUNT                                 3:3 /* C--VF */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_L1P_ENTRY_COUNT_DONE                     0x00000000 /* C---V */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_L1_TO_RECOVERY_COUNT                            4:4 /* C--VF */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_L1_TO_RECOVERY_COUNT_DONE                0x00000000 /* C---V */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_L0_TO_RECOVERY_COUNT                            5:5 /* C--VF */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_L0_TO_RECOVERY_COUNT_DONE                0x00000000 /* C---V */
#define NV_XVE_ERROR_COUNTER_RESET_CORR_ERROR_COUNT                                     6:6 /* RWCVF */
#define NV_XVE_ERROR_COUNTER_RESET_CORR_ERROR_COUNT_TRIGGER                      0x00000001 /* -W--T */
#define NV_XVE_ERROR_COUNTER_RESET_CORR_ERROR_COUNT_DONE                         0x00000000 /* R-C-V */
#define NV_XVE_ERROR_COUNTER_RESET_CORR_ERROR_COUNT_PENDING                      0x00000001 /* R---V */
#define NV_XVE_ERROR_COUNTER_RESET_NON_FATAL_ERROR_COUNT                                7:7 /* RWCVF */
#define NV_XVE_ERROR_COUNTER_RESET_NON_FATAL_ERROR_COUNT_TRIGGER                 0x00000001 /* -W--T */
#define NV_XVE_ERROR_COUNTER_RESET_NON_FATAL_ERROR_COUNT_DONE                    0x00000000 /* R-C-V */
#define NV_XVE_ERROR_COUNTER_RESET_NON_FATAL_ERROR_COUNT_PENDING                 0x00000001 /* R---V */
#define NV_XVE_ERROR_COUNTER_RESET_FATAL_ERROR_COUNT                                    8:8 /* RWCVF */
#define NV_XVE_ERROR_COUNTER_RESET_FATAL_ERROR_COUNT_TRIGGER                     0x00000001 /* -W--T */
#define NV_XVE_ERROR_COUNTER_RESET_FATAL_ERROR_COUNT_DONE                        0x00000000 /* R-C-V */
#define NV_XVE_ERROR_COUNTER_RESET_FATAL_ERROR_COUNT_PENDING                     0x00000001 /* R---V */
#define NV_XVE_ERROR_COUNTER_RESET_UNSUPP_REQ_COUNT                                     9:9 /* RWCVF */
#define NV_XVE_ERROR_COUNTER_RESET_UNSUPP_REQ_COUNT_TRIGGER                      0x00000001 /* -W--T */
#define NV_XVE_ERROR_COUNTER_RESET_UNSUPP_REQ_COUNT_DONE                         0x00000000 /* R-C-V */
#define NV_XVE_ERROR_COUNTER_RESET_UNSUPP_REQ_COUNT_PENDING                      0x00000001 /* R---V */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_DEEP_L1_ENTRY_COUNT                           10:10 /* C--VF */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_DEEP_L1_ENTRY_COUNT_DONE                 0x00000000 /* C---V */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_ASLM_COUNT                                    11:11 /* C--VF */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_ASLM_COUNT_DONE                          0x00000000 /* C---V */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_NAK_COUNT                                     12:12 /* C--VF */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_NAK_COUNT_DONE                           0x00000000 /* C---V */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_REPLAY_COUNT                                  13:13 /* C--VF */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_REPLAY_COUNT_DONE                        0x00000000 /* C---V */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_RECOVERY_COUNT                                14:14 /* C--VF */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_RECOVERY_COUNT_DONE                      0x00000000 /* C---V */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_CLKREQ_DEASSERT_ENTRY_COUNT                   15:15 /* C--VF */
#define NV_XVE_ERROR_COUNTER_RESET_RSVD_CLKREQ_DEASSERT_ENTRY_COUNT_DONE         0x00000000 /* C---V */
#define NV_XVE_PRI_XVE_CG                          0x000004E8 /* RW-4R */
#define NV_XVE_PRI_XVE_CG_IDLE_CG_DLY_CNT                 5:0 /* RWIVF */
#define NV_XVE_PRI_XVE_CG_IDLE_CG_DLY_CNT_HWINIT   0x00000000 /* RWI-V */
#define NV_XVE_PRI_XVE_CG_IDLE_CG_DLY_CNT__PROD    0x00000004 /* RW--V */
#define NV_XVE_PRI_XVE_CG_IDLE_CG_EN                      6:6 /* RWIVF */
#define NV_XVE_PRI_XVE_CG_IDLE_CG_EN_ENABLED       0x00000001 /* RW--V */
#define NV_XVE_PRI_XVE_CG_IDLE_CG_EN_DISABLED      0x00000000 /* RWI-V */
#define NV_XVE_PRI_XVE_CG_IDLE_CG_EN__PROD         0x00000001 /* RW--V */
#define NV_XVE_PRI_XVE_CG_STATE_CG_EN                     7:7 /*       */
#define NV_XVE_PRI_XVE_CG_STATE_CG_EN_ENABLED      0x00000001 /*       */
#define NV_XVE_PRI_XVE_CG_STATE_CG_EN_DISABLED     0x00000000 /*       */
#define NV_XVE_PRI_XVE_CG_STATE_CG_EN__PROD        0x00000000 /*       */
#define NV_XVE_PRI_XVE_CG_STALL_CG_DLY_CNT               13:8 /*       */
#define NV_XVE_PRI_XVE_CG_STALL_CG_DLY_CNT_HWINIT  0x00000000 /*       */
#define NV_XVE_PRI_XVE_CG_STALL_CG_DLY_CNT__PROD   0x00000000 /*       */
#define NV_XVE_PRI_XVE_CG_STALL_CG_EN                   14:14 /* RWIVF */
#define NV_XVE_PRI_XVE_CG_STALL_CG_EN_ENABLED      0x00000001 /* RW--V */
#define NV_XVE_PRI_XVE_CG_STALL_CG_EN_DISABLED     0x00000000 /* RWI-V */
#define NV_XVE_PRI_XVE_CG_STALL_CG_EN__PROD        0x00000000 /* RW--V */
#define NV_XVE_PRI_XVE_CG_QUIESCENT_CG_EN               15:15 /*       */
#define NV_XVE_PRI_XVE_CG_QUIESCENT_CG_EN_ENABLED  0x00000001 /*       */
#define NV_XVE_PRI_XVE_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /*       */
#define NV_XVE_PRI_XVE_CG_QUIESCENT_CG_EN__PROD    0x00000000 /*       */
#define NV_XVE_PRI_XVE_CG_WAKEUP_DLY_CNT                19:16 /* RWIVF */
#define NV_XVE_PRI_XVE_CG_WAKEUP_DLY_CNT_HWINIT    0x00000000 /* RWI-V */
#define NV_XVE_PRI_XVE_CG_WAKEUP_DLY_CNT__PROD     0x00000000 /* RW--V */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_CNT                 23:20 /*       */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_CNT_FULLSPEED  0x0000000f /*       */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_CNT__PROD      0x00000000 /*       */
#define NV_XVE_PRI_XVE_CG_DI_DT_SKEW_VAL                27:24 /*       */
#define NV_XVE_PRI_XVE_CG_DI_DT_SKEW_VAL_HWINIT    0x00000000 /*       */
#define NV_XVE_PRI_XVE_CG_DI_DT_SKEW_VAL__PROD     0x00000000 /*       */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_EN                  28:28 /*       */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_EN_ENABLED     0x00000001 /*       */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_EN_DISABLED    0x00000000 /*       */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_EN__PROD       0x00000000 /*       */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_SW_OVER             29:29 /*       */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_SW_OVER_EN     0x00000001 /*       */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_SW_OVER_DIS    0x00000000 /*       */
#define NV_XVE_PRI_XVE_CG_THROT_CLK_SW_OVER__PROD  0x00000000 /*       */
#define NV_XVE_PRI_XVE_CG_PAUSE_CG_EN                   30:30 /*       */
#define NV_XVE_PRI_XVE_CG_PAUSE_CG_EN_ENABLED      0x00000001 /*       */
#define NV_XVE_PRI_XVE_CG_PAUSE_CG_EN_DISABLED     0x00000000 /*       */
#define NV_XVE_PRI_XVE_CG_PAUSE_CG_EN__PROD        0x00000000 /*       */
#define NV_XVE_PRI_XVE_CG_HALT_CG_EN                    31:31 /*       */
#define NV_XVE_PRI_XVE_CG_HALT_CG_EN_ENABLED       0x00000001 /*       */
#define NV_XVE_PRI_XVE_CG_HALT_CG_EN_DISABLED      0x00000000 /*       */
#define NV_XVE_PRI_XVE_CG_HALT_CG_EN__PROD         0x00000000 /*       */
#define NV_XVE_PRI_XVE_CG1                               0x000004EC /* RW-4R */
#define NV_XVE_PRI_XVE_CG1_MONITOR_CG_EN                      0:0 /* RWIVF */
#define NV_XVE_PRI_XVE_CG1_MONITOR_CG_EN_ENABLED       0x00000001 /* RW--V */
#define NV_XVE_PRI_XVE_CG1_MONITOR_CG_EN_DISABLED      0x00000000 /* RWI-V */
#define NV_XVE_PRI_XVE_CG1_MONITOR_CG_EN__PROD         0x00000000 /* RW--V */
#define NV_XVE_PRI_XVE_CG1_SLCG                            17:1 /* RWIVF */
#define NV_XVE_PRI_XVE_CG1_SLCG_ENABLED                0x00000000 /* RW--V */
#define NV_XVE_PRI_XVE_CG1_SLCG_DISABLED               0x0001FFFF /* RWI-V */
#define NV_XVE_PRI_XVE_CG1_SLCG__PROD                  0x00000000 /* RW--V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE                                     0x0000060C /* R--4R */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_NV_GEN2_PCIE                               0:0 /* R-CVF */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_NV_GEN2_PCIE_CAPABLE                0x00000001 /* R-C-V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_NV_GEN2_PCIE_DISABLED               0x00000000 /* R---V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_PSEUDO_VC                                  2:2 /* C--VF */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_PSEUDO_VC_NOT_CAPABLE               0x00000000 /* C---V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_RSVD_0                                    10:3 /* C--VF */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_RSVD_0_INIT                         0x00000000 /* C---V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_FB_SIZE_OVERRIDE                         11:11 /* R-CVF */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_FB_SIZE_OVERRIDE_SUPPORTED          0x00000001 /* R-C-V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_FB_SIZE_OVERRIDE_NOT_SUPPORTED      0x00000000 /* R---V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_NV_GEN3_PCIE                             12:12 /* R-CVF */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_NV_GEN3_PCIE_CAPABLE                0x00000001 /* R-C-V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_NV_GEN3_PCIE_DISABLED               0x00000000 /* R---V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_RSVD_1                                   31:13 /* C--VF */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_DEVICE_RSVD_1_INIT                         0x00000000 /* C---V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY                                     0x00000610 /* RW-4R */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_NV_GEN2_PCIE                               0:0 /* RWCVF */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_NV_GEN2_PCIE_NOT_CAPABLE            0x00000000 /* RWC-V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_NV_GEN2_PCIE_CAPABLE                0x00000001 /* RW--V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_MULTIBYTE_ENABLE_WRITE                     1:1 /* RWCVF */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_MULTIBYTE_ENABLE_WRITE_NOT_CAPABLE  0x00000000 /* RWC-V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_MULTIBYTE_ENABLE_WRITE_CAPABLE      0x00000001 /* RW--V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_RSVD_0                                     6:2 /* RWCVF */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_RSVD_0_INIT                         0x00000000 /* RWC-V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL                      10:7 /* RWCVF */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_INIT           0x00000000 /* RWC-V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_64MB           0x00000000 /* RW--V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_128MB          0x00000001 /* RW--V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_256MB          0x00000002 /* RW--V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_512MB          0x00000003 /* RW--V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_1GB            0x00000004 /* RW--V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_2GB            0x00000005 /* RW--V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_4GB            0x00000006 /* RW--V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_8GB            0x00000007 /* RW--V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_16GB           0x00000008 /* RW--V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_32GB           0x00000009 /* RW--V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_64GB           0x0000000a /* RW--V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_128GB          0x0000000b /* RW--V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_256GB          0x0000000c /* RW--V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_512GB          0x0000000d /* RW--V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_1TB            0x0000000e /* RW--V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_VAL_RSVD           0x0000000f /* RW--V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_EN                      11:11 /* RWCVF */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_EN_CAPABLE         0x00000001 /* RW--V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_FB_SIZE_OVERRIDE_EN_NOT_CAPABLE     0x00000000 /* RWC-V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_NV_GEN3_PCIE                             12:12 /* RWCVF */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_NV_GEN3_PCIE_NOT_CAPABLE            0x00000000 /* RWC-V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_NV_GEN3_PCIE_CAPABLE                0x00000001 /* RW--V */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_RSVD_1                                   31:13 /* RWCVF */
#define NV_XVE_VSEC_NVIDIA_SPECIFIC_FEATURES_HIERARCHY_RSVD_1_INIT                         0x00000000 /* RWC-V */
#define NV_XVE_TCIPHER_KEY(i)                         (0x00000624+(i)*8) /* -W-4A */
#define NV_XVE_TCIPHER_KEY__SIZE_1                                    4  /*       */
#define NV_XVE_TCIPHER_KEY_VALUE                                   31:0  /* -WCVF */
#define NV_XVE_TCIPHER_KEY_VALUE_INIT                        0x00000000  /* -WC-V */
#define NV_XVE_PRIV_XV_BLKCG2                                                     0x00000658 /* RW-4R */
#define NV_XVE_PRIV_XV_BLKCG2_HOST2XV_HOST_IDLE_WAKE_EN                                  0:0 /* RWIVF */
#define NV_XVE_PRIV_XV_BLKCG2_HOST2XV_HOST_IDLE_WAKE_EN_ENABLED                   0x00000001 /* RWI-V */
#define NV_XVE_PRIV_XV_BLKCG2_HOST2XV_HOST_IDLE_WAKE_EN_DISABLED                  0x00000000 /* RW--V */
#define NV_XVE_PRIV_XV_BLKCG2_RSVD_HOST2XV_FORCE_CLK_ON_WAKE_EN                          1:1 /* C--VF */
#define NV_XVE_PRIV_XV_BLKCG2_RSVD_HOST2XV_FORCE_CLK_ON_WAKE_EN_ENABLED           0x00000001 /* C---V */
#define NV_XVE_PRIV_XV_BLKCG2_UPSTREAM_REQ_WAKE_EN                                       2:2 /* RWIVF */
#define NV_XVE_PRIV_XV_BLKCG2_UPSTREAM_REQ_WAKE_EN_ENABLED                        0x00000001 /* RWI-V */
#define NV_XVE_PRIV_XV_BLKCG2_UPSTREAM_REQ_WAKE_EN_DISABLED                       0x00000000 /* RW--V */
#define NV_XVE_PRIV_XV_BLKCG2_RSVD_XP_PAD_IDLE_WAKE_EN                                   3:3 /* C--VF */
#define NV_XVE_PRIV_XV_BLKCG2_RSVD_XP_PAD_IDLE_WAKE_EN_DISABLED                   0x00000000 /* C---V */
#define NV_XVE_PRIV_XV_BLKCG2_CONFIG0_UPDATE_WAKE_EN                                     4:4 /* RWIVF */
#define NV_XVE_PRIV_XV_BLKCG2_CONFIG0_UPDATE_WAKE_EN_ENABLED                      0x00000001 /* RWI-V */
#define NV_XVE_PRIV_XV_BLKCG2_CONFIG0_UPDATE_WAKE_EN_DISABLED                     0x00000000 /* RW--V */
#define NV_XVE_PRIV_XV_BLKCG2_CONFIG1_UPDATE_WAKE_EN                                     5:5 /* RWIVF */
#define NV_XVE_PRIV_XV_BLKCG2_CONFIG1_UPDATE_WAKE_EN_ENABLED                      0x00000001 /* RWI-V */
#define NV_XVE_PRIV_XV_BLKCG2_CONFIG1_UPDATE_WAKE_EN_DISABLED                     0x00000000 /* RW--V */
#define NV_XVE_PRIV_XV_BLKCG2_FN0_INTR_PENDING_WAKE_EN                                   8:8 /* RWIVF */
#define NV_XVE_PRIV_XV_BLKCG2_FN0_INTR_PENDING_WAKE_EN_ENABLED                    0x00000001 /* RWI-V */
#define NV_XVE_PRIV_XV_BLKCG2_FN0_INTR_PENDING_WAKE_EN_DISABLED                   0x00000000 /* RW--V */
#define NV_XVE_PRIV_XV_BLKCG2_FN1_INTR_PENDING_WAKE_EN                                   9:9 /* RWIVF */
#define NV_XVE_PRIV_XV_BLKCG2_FN1_INTR_PENDING_WAKE_EN_ENABLED                    0x00000001 /* RWI-V */
#define NV_XVE_PRIV_XV_BLKCG2_FN1_INTR_PENDING_WAKE_EN_DISABLED                   0x00000000 /* RW--V */
#define NV_XVE_PRIV_XV_BLKCG2_FN0_EOI_PENDING_WAKE_EN                                  10:10 /* RWIVF */
#define NV_XVE_PRIV_XV_BLKCG2_FN0_EOI_PENDING_WAKE_EN_ENABLED                     0x00000001 /* RWI-V */
#define NV_XVE_PRIV_XV_BLKCG2_FN0_EOI_PENDING_WAKE_EN_DISABLED                    0x00000000 /* RW--V */
#define NV_XVE_PRIV_XV_BLKCG2_FN1_EOI_PENDING_WAKE_EN                                  11:11 /* RWIVF */
#define NV_XVE_PRIV_XV_BLKCG2_FN1_EOI_PENDING_WAKE_EN_ENABLED                     0x00000001 /* RWI-V */
#define NV_XVE_PRIV_XV_BLKCG2_FN1_EOI_PENDING_WAKE_EN_DISABLED                    0x00000000 /* RW--V */
#define NV_XVE_CYA_2                                        0x00000704 /* RW-4R */
#define NV_XVE_CYA_2_RSVD                                         31:0 /* RWCVF */
#define NV_XVE_CYA_2_RSVD_INIT                              0x00000000 /* RWC-V */
#define NV_XVE_CYA_3                                                0x00000708 /* RW-4R */
#define NV_XVE_CYA_3_CP_XSUBCH_STARVATION_FIX                              0:0 /* RWCVF */
#define NV_XVE_CYA_3_CP_XSUBCH_STARVATION_FIX_DISABLED              0x00000000 /* RW--V */
#define NV_XVE_CYA_3_CP_XSUBCH_STARVATION_FIX_ENABLED               0x00000001 /* RWC-V */
#define NV_XVE_CYA_3_CP_XSUBCH_SPLIT_RAM_X_FIX                             1:1 /* RWCVF */
#define NV_XVE_CYA_3_CP_XSUBCH_SPLIT_RAM_X_FIX_ENABLED              0x00000000 /* RWC-V */
#define NV_XVE_CYA_3_CP_XSUBCH_SPLIT_RAM_X_FIX_DISABLED             0x00000001 /* RW--V */
#define NV_XVE_CYA_3_BLOCK_UPSTREAM_IN_NON_D0_PWR_STATES                   2:2 /* RWCVF */
#define NV_XVE_CYA_3_BLOCK_UPSTREAM_IN_NON_D0_PWR_STATES_DISABLED   0x00000000 /* RW--V */
#define NV_XVE_CYA_3_BLOCK_UPSTREAM_IN_NON_D0_PWR_STATES_ENABLED    0x00000001 /* RWC-V */
#define NV_XVE_CYA_3_BUS_MASTER_DIS_BLOCK_UPSTREAM_P2P                     3:3 /* RWCVF */
#define NV_XVE_CYA_3_BUS_MASTER_DIS_BLOCK_UPSTREAM_P2P_DISABLED     0x00000000 /* RW--V */
#define NV_XVE_CYA_3_BUS_MASTER_DIS_BLOCK_UPSTREAM_P2P_ENABLED      0x00000001 /* RWC-V */
#define NV_XVE_CYA_3_US_P2P_CPL_STARVATION_FIX                             5:5 /* RWCVF */
#define NV_XVE_CYA_3_US_P2P_CPL_STARVATION_FIX_DISABLED             0x00000000 /* RW--V */
#define NV_XVE_CYA_3_US_P2P_CPL_STARVATION_FIX_ENABLED              0x00000001 /* RWC-V */
#define NV_XVE_CYA_3_US_P2P_PW_STARVATION_FIX                              6:6 /* RWCVF */
#define NV_XVE_CYA_3_US_P2P_PW_STARVATION_FIX_DISABLED              0x00000000 /* RW--V */
#define NV_XVE_CYA_3_US_P2P_PW_STARVATION_FIX_ENABLED               0x00000001 /* RWC-V */
#define NV_XVE_CYA_3_MSGD_INVALID_TYPE_ERROR                               7:7 /* RWCVF */
#define NV_XVE_CYA_3_MSGD_INVALID_TYPE_ERROR_DISABLED               0x00000000 /* RW--V */
#define NV_XVE_CYA_3_MSGD_INVALID_TYPE_ERROR_ENABLED                0x00000001 /* RWC-V */
#define NV_XVE_CYA_3_LEGACY_ENDPOINT_DEVICE                                8:8 /* RWCVF */
#define NV_XVE_CYA_3_LEGACY_ENDPOINT_DEVICE_DISABLED                0x00000000 /* RWC-V */
#define NV_XVE_CYA_3_LEGACY_ENDPOINT_DEVICE_ENABLED                 0x00000001 /* RW--V */
#define NV_XVE_CYA_3_HIDE_OBFF_CAP                                         9:9 /* RWCVF */
#define NV_XVE_CYA_3_HIDE_OBFF_CAP_INIT                             0x00000000 /* RWC-V */
#define NV_XVE_CYA_3_HIDE_OBFF_CAP_ENABLE                           0x00000001 /* RW--V */
#define NV_XVE_CYA_3_HIDE_OBFF_CAP_DISABLE                          0x00000000 /* RW--V */
#define NV_XVE_CYA_3_UC_ARB1_STARVATION_FIX                              10:10 /* RWCVF */
#define NV_XVE_CYA_3_UC_ARB1_STARVATION_FIX_INIT                    0x00000000 /* RWC-V */
#define NV_XVE_CYA_3_UC_ARB1_STARVATION_FIX_ENABLE                  0x00000001 /* RW--V */
#define NV_XVE_CYA_3_UC_ARB1_STARVATION_FIX_DISABLE                 0x00000000 /* RW--V */
#define NV_XVE_CYA_3_P2P_8DW_FLUSH_LEN                                   11:11 /* RWCVF */
#define NV_XVE_CYA_3_P2P_8DW_FLUSH_LEN_INIT                         0x00000000 /* RWC-V */
#define NV_XVE_CYA_3_P2P_8DW_FLUSH_LEN_ENABLE                       0x00000001 /* RW--V */
#define NV_XVE_CYA_3_P2P_8DW_FLUSH_LEN_DISABLE                      0x00000000 /* RW--V */
#define NV_XVE_CYA_3_TXB_CREDIT_CHECK_FIX                                13:13 /* RWCVF */
#define NV_XVE_CYA_3_TXB_CREDIT_CHECK_FIX_INIT                      0x00000001 /* RWC-V */
#define NV_XVE_CYA_3_TXB_CREDIT_CHECK_FIX_ENABLE                    0x00000001 /* RW--V */
#define NV_XVE_CYA_3_TXB_CREDIT_CHECK_FIX_DISABLE                   0x00000000 /* RW--V */
#define NV_XVE_CYA_3_UC_ARB1_WLRU_FIX                                    14:14 /* RWCVF */
#define NV_XVE_CYA_3_UC_ARB1_WLRU_FIX_ENABLED                       0x00000001 /* RW--V */
#define NV_XVE_CYA_3_UC_ARB1_WLRU_FIX_DISABLED                      0x00000000 /* RW--V */
#define NV_XVE_CYA_3_UC_ARB1_WLRU_FIX_DEFAULT                       0x00000001 /* RWC-V */
#define NV_XVE_CYA_3_TXB_ARBCTL_STARVATION_FIX                           15:15 /* RWCVF */
#define NV_XVE_CYA_3_TXB_ARBCTL_STARVATION_FIX_INIT                 0x00000001 /* RWC-V */
#define NV_XVE_CYA_3_TXB_ARBCTL_STARVATION_FIX_ENABLE               0x00000001 /* RW--V */
#define NV_XVE_CYA_3_TXB_ARBCTL_STARVATION_FIX_DISABLE              0x00000000 /* RW--V */
#define NV_XVE_CYA_3_P2P_ESCAPED_UCPL_FIX                                16:16 /* RWCVF */
#define NV_XVE_CYA_3_P2P_ESCAPED_UCPL_FIX_INIT                      0x00000001 /* RWC-V */
#define NV_XVE_CYA_3_P2P_ESCAPED_UCPL_FIX_ENABLE                    0x00000001 /* RW--V */
#define NV_XVE_CYA_3_P2P_ESCAPED_UCPL_FIX_DISABLE                   0x00000000 /* RW--V */
#define NV_XVE_CYA_3_STRAP_DEVID_SEL_OVERRIDE_EN                         19:19 /* RWCVF */
#define NV_XVE_CYA_3_STRAP_DEVID_SEL_OVERRIDE_EN_INIT               0x00000000 /* RWC-V */
#define NV_XVE_CYA_3_STRAP_DEVID_SEL_OVERRIDE_EN_ENABLE             0x00000001 /* RW--V */
#define NV_XVE_CYA_3_STRAP_DEVID_SEL_OVERRIDE_EN_DISABLE            0x00000000 /* RW--V */
#define NV_XVE_CYA_3_STRAP_DEVID_SEL_OVERRIDE_VAL                        20:20 /* RWCVF */
#define NV_XVE_CYA_3_STRAP_DEVID_SEL_OVERRIDE_VAL_INIT              0x00000000 /* RWC-V */
#define NV_XVE_CYA_3_STRAP_DEVID_SEL_OVERRIDE_VAL_ONE               0x00000001 /* RW--V */
#define NV_XVE_CYA_3_STRAP_DEVID_SEL_OVERRIDE_VAL_ZERO              0x00000000 /* RW--V */
#define NV_XVE_CYA_3_GEN4L_CAP_STATUS_CONFIG                             21:21 /* RWCVF */
#define NV_XVE_CYA_3_GEN4L_CAP_STATUS_CONFIG_INIT                   0x00000000 /* RWC-V */
#define NV_XVE_CYA_3_GEN4L_CAP_STATUS_CONFIG_8GTS_MODE              0x00000000 /* R---V */
#define NV_XVE_CYA_3_GEN4L_CAP_STATUS_CONFIG_16GTS_MODE             0x00000001 /* R---V */
#define NV_XVE_CYA_3_SKIP_UR_INCR_CE_CNT                                 22:22 /* RWCVF */
#define NV_XVE_CYA_3_SKIP_UR_INCR_CE_CNT_INIT                       0x00000000 /* RWC-V */
#define NV_XVE_CYA_3_RSVD                                                31:23 /* RWCVF */
#define NV_XVE_CYA_3_RSVD_INIT                                      0x00000000 /* RWC-V */
#define NV_XVE_DEBUG_3                                              0x00000714 /* RW-4R */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_EXP                         3:0 /* RWCVF */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_EXP_MIN              0x00000000 /* RW--V */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_EXP_MAX              0x0000000f /* RW--V */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_EXP_DEFAULT          0x0000000a /* RWC-V */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_MAN                        10:4 /* RWCVF */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_MAN_128              0x00000000 /* RW--V */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_MAN_160              0x00000021 /* RW--V */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_MAN_196              0x00000040 /* RW--V */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_MAN_224              0x00000060 /* RW--V */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_MAN_DEFAULT          0x00000000 /* RWC-V */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_EN                        11:11 /* RWCVF */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_EN_DISABLED          0x00000000 /* RW--V */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_EN_ENABLED           0x00000001 /* RW--V */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_EN_DEFAULT           0x00000001 /* RWC-V */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_STATUS0                   12:12 /* RWCVF */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_STATUS0_NOT_PENDING  0x00000000 /* R-C-V */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_STATUS0_PENDING      0x00000001 /* R---V */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_STATUS0_RESET        0x00000001 /* -W--C */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_STATUS1                   13:13 /* RWCVF */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_STATUS1_NOT_PENDING  0x00000000 /* R-C-V */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_STATUS1_PENDING      0x00000001 /* R---V */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_STATUS1_RESET        0x00000001 /* -W--C */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_TO_INTR                   14:14 /* RWCVF */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_TO_INTR_DISABLED     0x00000000 /* RW--V */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_TO_INTR_ENABLED      0x00000001 /* RW--V */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_TO_INTR_DEFAULT      0x00000001 /* RWC-V */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_CYA1_PW_DROP               15:15 /* RWCVF */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_CYA1_PW_DROP_EN       0x00000001 /* RW--V */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_CYA1_PW_DROP_DIS      0x00000000 /* RWC-V */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_CYA2_PW_DROP               16:16 /* RWCVF */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_CYA2_PW_DROP_EN       0x00000001 /* RW--V */
#define NV_XVE_DEBUG_3_POSTED_DEADLOCK_TIMEOUT_CYA2_PW_DROP_DIS      0x00000000 /* RWC-V */
#define NV_XVE_DEBUG_3_SPARE                                             31:17 /* RWCVF */
#define NV_XVE_DEBUG_3_SPARE_DEFAULT                                0x00000000 /* RWC-V */
#define NV_XVE_CPLTO_HDR0                                 0x00000840 /* R-C4R */
#define NV_XVE_CPLTO_HDR0_SYSMEM                                 0:0 /* R-CVF */
#define NV_XVE_CPLTO_HDR0_SYSMEM_INIT                     0x00000000 /* R-C-V */
#define NV_XVE_CPLTO_HDR0_PEERMEM                                1:1 /* R-CVF */
#define NV_XVE_CPLTO_HDR0_PEERMEM_INIT                    0x00000000 /* R-C-V */
#define NV_XVE_CPLTO_HDR0_PEER_ID                                5:2 /* R-CVF */
#define NV_XVE_CPLTO_HDR0_PEER_ID_INIT                    0x00000000 /* R-C-V */
#define NV_XVE_CPLTO_HDR0_FN                                    10:8 /* R-CVF */
#define NV_XVE_CPLTO_HDR0_FN_INIT                         0x00000000 /* R-C-V */
#define NV_XVE_CPLTO_HDR0_TC                                   13:11 /* R-CVF */
#define NV_XVE_CPLTO_HDR0_TC_INIT                         0x00000000 /* R-C-V */
#define NV_XVE_CPLTO_HDR0_NO_SNOOP                             14:14 /* R-CVF */
#define NV_XVE_CPLTO_HDR0_NO_SNOOP_INIT                   0x00000000 /* R-C-V */
#define NV_XVE_CPLTO_HDR0_RELAXED_ORD                          15:15 /* R-CVF */
#define NV_XVE_CPLTO_HDR0_RELAXED_ORD_INIT                0x00000000 /* R-C-V */
#define NV_XVE_CPLTO_HDR0_LENGTH                               23:16 /* R-CVF */
#define NV_XVE_CPLTO_HDR0_LENGTH_INIT                     0x00000000 /* R-C-V */
#define NV_XVE_CPLTO_HDR0_TAG                                  31:24 /* R-CVF */
#define NV_XVE_CPLTO_HDR0_TAG_INIT                        0x00000000 /* R-C-V */
#define NV_XVE_CPLTO_HDR1                                 0x00000844 /* R-C4R */
#define NV_XVE_CPLTO_HDR1_ADDR_DW0                              31:0 /* R-CVF */
#define NV_XVE_CPLTO_HDR1_ADDR_DW0_INIT                   0x00000844 /* R-C-V */
#define NV_XVE_CPLTO_MISC                                 0x00000848 /* RWC4R */
#define NV_XVE_CPLTO_MISC_SYSMEM                                 0:0 /* R-CVF */
#define NV_XVE_CPLTO_MISC_SYSMEM_INIT                     0x00000000 /* R-C-V */
#define NV_XVE_CPLTO_MISC_PEERMEM                                1:1 /* R-CVF */
#define NV_XVE_CPLTO_MISC_PEERMEM_INIT                    0x00000000 /* R-C-V */
#define NV_XVE_CPLTO_MISC_PEER_ID                                4:2 /* R-CVF */
#define NV_XVE_CPLTO_MISC_PEER_ID_INIT                    0x00000000 /* R-C-V */
#define NV_XVE_CPLTO_MISC_FN                                     7:5 /* R-CVF */
#define NV_XVE_CPLTO_MISC_FN_INIT                         0x00000000 /* R-C-V */
#define NV_XVE_CPLTO_MISC_NO_SNOOP                               8:8 /* R-CVF */
#define NV_XVE_CPLTO_MISC_NO_SNOOP_INIT                   0x00000000 /* R-C-V */
#define NV_XVE_CPLTO_MISC_RELAXED_ORD                            9:9 /* R-CVF */
#define NV_XVE_CPLTO_MISC_RELAXED_ORD_INIT                0x00000000 /* R-C-V */
#define NV_XVE_CPLTO_MISC_LENGTH                               17:10 /* R-CVF */
#define NV_XVE_CPLTO_MISC_LENGTH_INIT                     0x00000000 /* R-C-V */
#define NV_XVE_CPLTO_MISC_ADDR_DW0_VLD                         18:18 /* RWCVF */
#define NV_XVE_CPLTO_MISC_ADDR_DW0_VLD_INIT               0x00000000 /* R-C-V */
#define NV_XVE_CPLTO_MISC_ADDR_DW0_VLD_CLEAR              0x00000001 /* -W--C */
#define NV_XVE_CPLTO_MISC_CYA_BYPASS_DCPWFIFO_FULL_CHECK       30:30 /* RWCVF */
#define NV_XVE_CPLTO_MISC_CYA_BYPASS_DCPWFIFO_FULL_CHECK_INIT   0x00000001 /* RWC-V */
#define NV_XVE_CPLTO_MISC_UC2TXB_INTF_VIOLATION                31:31 /* RWCVF */
#define NV_XVE_CPLTO_MISC_UC2TXB_INTF_VIOLATION_INIT      0x00000000 /* R-C-V */
#define NV_XVE_CPLTO_MISC_UC2TXB_INTF_VIOLATION_CLEAR     0x00000001 /* -W--C */
#define NV_XVE_ERROR_COUNTER1                                     0x00000854 /* R--4R */
#define NV_XVE_ERROR_COUNTER1_CORR_ERROR_COUNT_VALUE                    15:0 /* R-XVF */
#define NV_XVE_LTR_HIGH_LATENCY                                                0x00000A10 /* RW-4R */
#define NV_XVE_LTR_HIGH_LATENCY_SNOOP_LATENCY_VALUE                                   9:0 /* RWCVF */
#define NV_XVE_LTR_HIGH_LATENCY_SNOOP_LATENCY_VALUE_INIT                       0x000000FA /* RWC-V */
#define NV_XVE_LTR_HIGH_LATENCY_SNOOP_LATENCY_SCALE                                 12:10 /* RWCVF */
#define NV_XVE_LTR_HIGH_LATENCY_SNOOP_LATENCY_SCALE_INIT                       0x00000001 /* RWC-V */
#define NV_XVE_LTR_HIGH_LATENCY_NO_SNOOP_LATENCY_VALUE                              25:16 /* RWCVF */
#define NV_XVE_LTR_HIGH_LATENCY_NO_SNOOP_LATENCY_VALUE_INIT                    0x000000FA /* RWC-V */
#define NV_XVE_LTR_HIGH_LATENCY_NO_SNOOP_LATENCY_SCALE                       28:26 /* RWCVF */
#define NV_XVE_LTR_HIGH_LATENCY_NO_SNOOP_LATENCY_SCALE_INIT                    0x00000001 /* RWC-V */
#define NV_XVE_LTR_LOW_LATENCY                                                0x00000A14 /* RW-4R */
#define NV_XVE_LTR_LOW_LATENCY_SNOOP_LATENCY_VALUE                                   9:0 /* RWCVF */
#define NV_XVE_LTR_LOW_LATENCY_SNOOP_LATENCY_VALUE_INIT                       0x000000FA /* RWC-V */
#define NV_XVE_LTR_LOW_LATENCY_SNOOP_LATENCY_SCALE                                 12:10 /* RWCVF */
#define NV_XVE_LTR_LOW_LATENCY_SNOOP_LATENCY_SCALE_INIT                       0x00000001 /* RWC-V */
#define NV_XVE_LTR_LOW_LATENCY_NO_SNOOP_LATENCY_VALUE                              25:16 /* RWCVF */
#define NV_XVE_LTR_LOW_LATENCY_NO_SNOOP_LATENCY_VALUE_INIT                    0x000000FA /* RWC-V */
#define NV_XVE_LTR_LOW_LATENCY_NO_SNOOP_LATENCY_SCALE                       28:26 /* RWCVF */
#define NV_XVE_LTR_LOW_LATENCY_NO_SNOOP_LATENCY_SCALE_INIT                    0x00000001 /* RWC-V */
#define NV_XVE_LTR_AZA_BW_MON_CTRL                                              0x00000A1C /* RW-4R */
#define NV_XVE_LTR_AZA_BW_MON_CTRL_INTERVAL_VALUE                                     15:0 /* RWCVF */
#define NV_XVE_LTR_AZA_BW_MON_CTRL_INTERVAL_VALUE_INIT                          0x00000000 /* RWC-V */
#define NV_XVE_LTR_AZA_BW_MON_CTRL_THRESHOLD                                         30:16 /* RWCVF */
#define NV_XVE_LTR_AZA_BW_MON_CTRL_THRESHOLD_INIT                               0x00000000 /* RWC-V */
#define NV_XVE_LTR_AZA_BW_MON_CTRL_ENABLE                                            31:31 /* RWCVF */
#define NV_XVE_LTR_AZA_BW_MON_CTRL_ENABLE_INIT                                  0x00000000 /* RWC-V */
#define NV_XVE_LTR_MSG_CTRL                                                     0x00000A20 /* RW-4R */
#define NV_XVE_LTR_MSG_CTRL_TRIGGER                                                    0:0 /* RWCVF */
#define NV_XVE_LTR_MSG_CTRL_TRIGGER_NOT_PENDING                                 0x00000000 /* RWC-V */
#define NV_XVE_LTR_MSG_CTRL_TRIGGER_PENDING                                     0x00000001 /* RW--V */
#define NV_XVE_LTR_MSG_CTRL_HIDE_LTR                                                   8:8 /* RWCVF */
#define NV_XVE_LTR_MSG_CTRL_HIDE_LTR_INIT                                       0x00000000 /* RWC-V */
#define NV_XVE_LTR_MSG_CTRL_D_STATE_CTRL                                               9:9 /* RWCVF */
#define NV_XVE_LTR_MSG_CTRL_D_STATE_CTRL_INIT                                   0x00000001 /* RWC-V */
#define NV_XVE_LTR_MSG_CTRL_NO_MSG_ON_LTR_EN                                         10:10 /* RWCVF */
#define NV_XVE_LTR_MSG_CTRL_NO_MSG_ON_LTR_EN_INIT                               0x00000001 /* RWC-V */
#define NV_XVE_LTR_LAST_MSG_SENT                                                0x00000A24 /* R--4R */
#define NV_XVE_LTR_LAST_MSG_SENT_SNOOP_LATENCY_VALUE                                   9:0 /* R-CVF */
#define NV_XVE_LTR_LAST_MSG_SENT_SNOOP_LATENCY_VALUE_INIT                       0x00000000 /* R-C-V */
#define NV_XVE_LTR_LAST_MSG_SENT_SNOOP_LATENCY_SCALE                                 12:10 /* R-CVF */
#define NV_XVE_LTR_LAST_MSG_SENT_SNOOP_LATENCY_SCALE_INIT                       0x00000000 /* R-C-V */
#define NV_XVE_LTR_LAST_MSG_SENT_SNOOP_LATENCY_REQUIREMENT                           13:13 /* R-CVF */
#define NV_XVE_LTR_LAST_MSG_SENT_SNOOP_LATENCY_REQUIREMENT_INIT                 0x00000000 /* R-C-V */
#define NV_XVE_LTR_LAST_MSG_SENT_NO_SNOOP_LATENCY_VALUE                              23:14 /* R-CVF */
#define NV_XVE_LTR_LAST_MSG_SENT_NO_SNOOP_LATENCY_VALUE_INIT                    0x00000000 /* R-C-V */
#define NV_XVE_LTR_LAST_MSG_SENT_NO_SNOOP_LATENCY_SCALE                         26:24 /* R-CVF */
#define NV_XVE_LTR_LAST_MSG_SENT_NO_SNOOP_LATENCY_SCALE_INIT                    0x00000000 /* R-C-V */
#define NV_XVE_LTR_LAST_MSG_SENT_NO_SNOOP_LATENCY_REQUIREMENT                     27:27 /* R-CVF */
#define NV_XVE_LTR_LAST_MSG_SENT_NO_SNOOP_LATENCY_REQUIREMENT_INIT              0x00000000 /* R-C-V */
#define NV_XVE_LTR_LAST_MSG_SENT_D_STATE_TRIGGERED                         28:28 /* R-CVF */
#define NV_XVE_LTR_LAST_MSG_SENT_D_STATE_TRIGGERED_INIT                     0x00000000 /* R-C-V */
#define NV_XVE_LTR_LAST_MSG_SENT_SW_TRIGGERED                             29:29 /* R-CVF */
#define NV_XVE_LTR_LAST_MSG_SENT_SW_TRIGGERED_INIT                        0x00000000 /* R-C-V */
#define NV_XVE_LTR_LAST_MSG_SENT_FB_BW_TRIGGERED                         30:30 /* R-CVF */
#define NV_XVE_LTR_LAST_MSG_SENT_FB_BW_TRIGGERED_INIT                              0x00000000 /* R-C-V */
#define NV_XVE_LTR_LAST_MSG_SENT_AZA_BW_TRIGGERED                         31:31 /* R-CVF */
#define NV_XVE_LTR_LAST_MSG_SENT_AZA_BW_TRIGGERED_INIT                      0x00000000 /* R-C-V */
#define NV_XVE_PCIE_UTIL_CTRL                                    0x00000A44 /* RW-4R */
#define NV_XVE_PCIE_UTIL_CTRL_ENABLE                                       0:0 /* RWCVF */
#define NV_XVE_PCIE_UTIL_CTRL_ENABLE_INIT                        0x00000000 /* RWC-V */
#define NV_XVE_PCIE_UTIL_CTRL_RESET_TX_BYTES_COUNT                      1:1 /* RWCVF */
#define NV_XVE_PCIE_UTIL_CTRL_RESET_TX_BYTES_COUNT_PENDING       0x00000001 /* RW--V */
#define NV_XVE_PCIE_UTIL_CTRL_RESET_TX_BYTES_COUNT_DONE          0x00000000 /* RWC-V */
#define NV_XVE_PCIE_UTIL_CTRL_RESET_RX_BYTES_COUNT                      2:2 /* RWCVF */
#define NV_XVE_PCIE_UTIL_CTRL_RESET_RX_BYTES_COUNT_PENDING       0x00000001 /* RW--V */
#define NV_XVE_PCIE_UTIL_CTRL_RESET_RX_BYTES_COUNT_DONE          0x00000000 /* RWC-V */
#define NV_XVE_PCIE_UTIL_CTRL_RESET_TX_L0_COUNT                         3:3 /* RWCVF */
#define NV_XVE_PCIE_UTIL_CTRL_RESET_TX_L0_COUNT_PENDING          0x00000001 /* RW--V */
#define NV_XVE_PCIE_UTIL_CTRL_RESET_TX_L0_COUNT_DONE             0x00000000 /* RWC-V */
#define NV_XVE_PCIE_UTIL_CTRL_RESET_RX_L0_COUNT                         4:4 /* RWCVF */
#define NV_XVE_PCIE_UTIL_CTRL_RESET_RX_L0_COUNT_PENDING          0x00000001 /* RW--V */
#define NV_XVE_PCIE_UTIL_CTRL_RESET_RX_L0_COUNT_DONE             0x00000000 /* RWC-V */
#define NV_XVE_PCIE_UTIL_CTRL_RESET_TX_L0S_COUNT                        5:5 /* RWCVF */
#define NV_XVE_PCIE_UTIL_CTRL_RESET_TX_L0S_COUNT_PENDING         0x00000001 /* RW--V */
#define NV_XVE_PCIE_UTIL_CTRL_RESET_TX_L0S_COUNT_DONE            0x00000000 /* RWC-V */
#define NV_XVE_PCIE_UTIL_CTRL_RESET_RX_L0S_COUNT                        6:6 /* RWCVF */
#define NV_XVE_PCIE_UTIL_CTRL_RESET_RX_L0S_COUNT_PENDING         0x00000001 /* RW--V */
#define NV_XVE_PCIE_UTIL_CTRL_RESET_RX_L0S_COUNT_DONE            0x00000000 /* RWC-V */
#define NV_XVE_PCIE_UTIL_CTRL_RESET_NON_L0_L0S_COUNT                    7:7 /* RWCVF */
#define NV_XVE_PCIE_UTIL_CTRL_RESET_NON_L0_L0S_COUNT_PENDING     0x00000001 /* RW--V */
#define NV_XVE_PCIE_UTIL_CTRL_RESET_NON_L0_L0S_COUNT_DONE        0x00000000 /* RWC-V */
#define NV_XVE_PCIE_UTIL_TX_BYTES                                     0x00000A48 /* RW-4R */
#define NV_XVE_PCIE_UTIL_TX_BYTES_COUNT                                     30:0 /* R--VF */
#define NV_XVE_PCIE_UTIL_TX_BYTES_COUNT_WRAP_STATUS                        31:31 /* RWCVF */
#define NV_XVE_PCIE_UTIL_TX_BYTES_COUNT_WRAP_STATUS_CLR_PENDING       0x00000001 /* RW--V */
#define NV_XVE_PCIE_UTIL_TX_BYTES_COUNT_WRAP_STATUS_CLR_DONE          0x00000000 /* RWC-V */
#define NV_XVE_PCIE_UTIL_RX_BYTES                                     0x00000A4C /* RW-4R */
#define NV_XVE_PCIE_UTIL_RX_BYTES_COUNT                                     30:0 /* R--VF */
#define NV_XVE_PCIE_UTIL_RX_BYTES_COUNT_WRAP_STATUS                        31:31 /* RWCVF */
#define NV_XVE_PCIE_UTIL_RX_BYTES_COUNT_WRAP_STATUS_CLR_PENDING       0x00000001 /* RW--V */
#define NV_XVE_PCIE_UTIL_RX_BYTES_COUNT_WRAP_STATUS_CLR_DONE          0x00000000 /* RWC-V */
#define NV_XVE_PCIE_UTIL_TX_L0                                        0x00000A50 /* RW-4R */
#define NV_XVE_PCIE_UTIL_TX_L0_COUNT                                     30:0 /* R--VF */
#define NV_XVE_PCIE_UTIL_TX_L0_COUNT_WRAP_STATUS                           31:31 /* RWCVF */
#define NV_XVE_PCIE_UTIL_TX_L0_COUNT_WRAP_STATUS_CLR_PENDING          0x00000001 /* RW--V */
#define NV_XVE_PCIE_UTIL_TX_L0_COUNT_WRAP_STATUS_CLR_DONE             0x00000000 /* RWC-V */
#define NV_XVE_PCIE_UTIL_RX_L0                                   0x00000A54 /* RW-4R */
#define NV_XVE_PCIE_UTIL_RX_L0_COUNT                                30:0 /* R--VF */
#define NV_XVE_PCIE_UTIL_RX_L0_COUNT_WRAP_STATUS                      31:31 /* RWCVF */
#define NV_XVE_PCIE_UTIL_RX_L0_COUNT_WRAP_STATUS_CLR_PENDING     0x00000001 /* RW--V */
#define NV_XVE_PCIE_UTIL_RX_L0_COUNT_WRAP_STATUS_CLR_DONE        0x00000000 /* RWC-V */
#define NV_XVE_PCIE_UTIL_TX_L0S                                        0x00000A58 /* RW-4R */
#define NV_XVE_PCIE_UTIL_TX_L0S_COUNT                                      30:0 /* R--VF */
#define NV_XVE_PCIE_UTIL_TX_L0S_COUNT_WRAP_STATUS                           31:31 /* RWCVF */
#define NV_XVE_PCIE_UTIL_TX_L0S_COUNT_WRAP_STATUS_CLR_PENDING          0x00000001 /* RW--V */
#define NV_XVE_PCIE_UTIL_TX_L0S_COUNT_WRAP_STATUS_CLR_DONE             0x00000000 /* RWC-V */
#define NV_XVE_PCIE_UTIL_RX_L0S                                        0x00000A60 /* RW-4R */
#define NV_XVE_PCIE_UTIL_RX_L0S_COUNT                                      30:0 /* R--VF */
#define NV_XVE_PCIE_UTIL_RX_L0S_COUNT_WRAP_STATUS                           31:31 /* RWCVF */
#define NV_XVE_PCIE_UTIL_RX_L0S_COUNT_WRAP_STATUS_CLR_PENDING          0x00000001 /* RW--V */
#define NV_XVE_PCIE_UTIL_RX_L0S_COUNT_WRAP_STATUS_CLR_DONE             0x00000000 /* RWC-V */
#define NV_XVE_PCIE_UTIL_NON_L0_L0S                                        0x00000A64 /* RW-4R */
#define NV_XVE_PCIE_UTIL_NON_L0_L0S_COUNT                                      30:0 /* R--VF */
#define NV_XVE_PCIE_UTIL_NON_L0_L0S_COUNT_WRAP_STATUS                           31:31 /* RWCVF */
#define NV_XVE_PCIE_UTIL_NON_L0_L0S_COUNT_WRAP_STATUS_CLR_PENDING          0x00000001 /* RW--V */
#define NV_XVE_PCIE_UTIL_NON_L0_L0S_COUNT_WRAP_STATUS_CLR_DONE             0x00000000 /* RWC-V */

--------------------------------------------------------------------------------
                         KEY LEGEND
--------------------------------------------------------------------------------

Each define in the .ref file has a 5 field code to say what kind of define it is: i.e. /* RW--R */
The following legend shows accepted values for each of the 5 fields:
  Read, Write, Internal State, Declaration/Size, and Define Indicator.

  Read
    ' ' = Other Information
    '-' = Field is part of a write-only register
    'C' = Value read is always the same, constant value line follows (C)
    'R' = Value is read


  Write
    ' ' = Other Information
    '-' = Must not be written (D), value ignored when written (R,A,F)
    'W' = Can be written


  Internal State
    ' ' = Other Information
    '-' = No internal state
    'X' = Internal state, initial value is unknown
    'I' = Internal state, initial value is known and follows (I), see "Reset Signal" section for signal.
    'E' = Internal state, initial value is known and follows (E), see "Reset Signal" section for signal.
    'B' = Internal state, initial value is known and follows (B), see "Reset Signal" section for signal.
    'C' = Internal state, initial value is known and follows (C), see "Reset Signal" section for signal.

    'V' = (legacy) Internal state, initialize at volatile reset
    'D' = (legacy) Internal state, default initial value at object creation (legacy: Only used in dev_ram.ref)
    'C' = (legacy) Internal state, initial value at object creation
    'C' = (legacy) Internal state, class-based initial value at object creation (legacy: Only used in dev_ram.ref)


  Declaration/Size
    ' ' = Other Information
    '-' = Does Not Apply
    'V' = Type is void
    'U' = Type is unsigned integer
    'S' = Type is signed integer
    'F' = Type is IEEE floating point
    '1' = Byte size (008)
    '2' = Short size (016)
    '3' = Three byte size (024)
    '4' = Word size (032)
    '8' = Double size (064)


  Define Indicator
    ' ' = Other Information
    'C' = Clear value
    'D' = Device
    'L' = Logical device.
    'M' = Memory
    'R' = Register
    'A' = Array of Registers
    'F' = Field
    'V' = Value
    'T' = Task
    'P' = Phantom Register

    'B' = (legacy) Bundle address
    'G' = (legacy) General purpose configuration register
    'C' = (legacy) Class

  Reset signal defaults for graphics engine registers.
    All graphics engine registers use the following defaults for reset signals:
     'E' = initialized with engine_reset_
     'I' = initialized with context_reset_
     'B' = initialized with reset_IB_dly_

  Reset signal
    For units that differ from the graphics engine defaults, the reset signals should be defined here: