Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -------------------------------------------------------------------------------- #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x00404488 /* RW-4R */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_NVCLASS 15:0 /* RWEVF */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_NVCLASS_INIT 0x0000 /* RWE-V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_METHOD_ADDR 27:16 /* RWEVF */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_METHOD_ADDR_INIT 0x000 /* RWE-V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_FEPIPE 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_FEPIPE_FE0 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_FEPIPE_FE1 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_READ 30:30 /* RWEVF */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_READ_DONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_READ_TRIGGER 0x1 /* -W--T */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_DONE 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 0x1 /* -W--T */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x0040448C /* RW-4R */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA_V 31:0 /* RWEVF */ #define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA_V_INIT 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR 0x00404490 /* RW-4R */ #define NV_PGRAPH_PRI_MME_HWW_ESR_MISSING_MACRO_DATA 0:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_MISSING_MACRO_DATA_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_MISSING_MACRO_DATA_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_EXTRA_MACRO_DATA 1:1 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_EXTRA_MACRO_DATA_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_EXTRA_MACRO_DATA_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_OPCODE 2:2 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_OPCODE_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_OPCODE_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_BRANCH_IN_DELAY_SLOT 3:3 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_BRANCH_IN_DELAY_SLOT_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_BRANCH_IN_DELAY_SLOT_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_MAX_INSTR_LIMIT 4:4 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_MAX_INSTR_LIMIT_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_MAX_INSTR_LIMIT_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INSTR_RAM_ACCESS_OUT_OF_BOUNDS 5:5 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INSTR_RAM_ACCESS_OUT_OF_BOUNDS_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INSTR_RAM_ACCESS_OUT_OF_BOUNDS_PENDING 0x1 /* R---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_STOP_ON_TRAP 29:29 /* RWEVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_STOP_ON_TRAP_DISABLED 0x0 /* RWE-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_STOP_ON_TRAP_ENABLED 0x1 /* RW--V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_V_0 0x0 /* -WE-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO 0x00404494 /* R--4R */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_PC 11:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_PC_INIT 0x000 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_VEID 27:28-6 /* C--VF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_VEID_0 0x00000000 /* C---V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_PC_VALID 28:28 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_PC_VALID_INIT 0x0 /* R-E-V */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO2 0x0040449c /* R--4R */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO2_IR 31:0 /* R-EVF */ #define NV_PGRAPH_PRI_MME_HWW_ESR_INFO2_IR_INIT 0x0 /* R-E-V */ -------------------------------------------------------------------------------- KEY LEGEND -------------------------------------------------------------------------------- Each define in the .ref file has a 5 field code to say what kind of define it is: i.e. /* RW--R */ The following legend shows accepted values for each of the 5 fields: Read, Write, Internal State, Declaration/Size, and Define Indicator. Read ' ' = Other Information '-' = Field is part of a write-only register 'C' = Value read is always the same, constant value line follows (C) 'R' = Value is read Write ' ' = Other Information '-' = Must not be written (D), value ignored when written (R,A,F) 'W' = Can be written Internal State ' ' = Other Information '-' = No internal state 'X' = Internal state, initial value is unknown 'I' = Internal state, initial value is known and follows (I), see "Reset Signal" section for signal. 'E' = Internal state, initial value is known and follows (E), see "Reset Signal" section for signal. 'B' = Internal state, initial value is known and follows (B), see "Reset Signal" section for signal. 'C' = Internal state, initial value is known and follows (C), see "Reset Signal" section for signal. 'V' = (legacy) Internal state, initialize at volatile reset 'D' = (legacy) Internal state, default initial value at object creation (legacy: Only used in dev_ram.ref) 'C' = (legacy) Internal state, initial value at object creation 'C' = (legacy) Internal state, class-based initial value at object creation (legacy: Only used in dev_ram.ref) Declaration/Size ' ' = Other Information '-' = Does Not Apply 'V' = Type is void 'U' = Type is unsigned integer 'S' = Type is signed integer 'F' = Type is IEEE floating point '1' = Byte size (008) '2' = Short size (016) '3' = Three byte size (024) '4' = Word size (032) '8' = Double size (064) Define Indicator ' ' = Other Information 'C' = Clear value 'D' = Device 'L' = Logical device. 'M' = Memory 'R' = Register 'A' = Array of Registers 'F' = Field 'V' = Value 'T' = Task 'P' = Phantom Register 'B' = (legacy) Bundle address 'G' = (legacy) General purpose configuration register 'C' = (legacy) Class Reset signal defaults for graphics engine registers. All graphics engine registers use the following defaults for reset signals: 'E' = initialized with engine_reset_ 'I' = initialized with context_reset_ 'B' = initialized with reset_IB_dly_ Reset signal For units that differ from the graphics engine defaults, the reset signals should be defined here: