4. Instructions¶
Tilus provides a set of instructions for writing GPU kernels. Instructions are available as methods
on the Script class and are called within the __call__ method of a script.
Instructions fall into two categories:
Generic instructions (
self.<instruction>) — common operations available on all GPUs, such as tensor creation, load/store, arithmetic, and synchronization.Instruction groups (
self.<group>.<instruction>) — specialized hardware-specific operations organized by the hardware unit they target, such as TMA, WGMMA, and TCGEN05.
4.1. Generic Instructions¶
Hint
Please submit a feature request if your kernel requires additional instructions.
4.1.1. Tensor Creation and Free¶
Create and manage tensors in register, shared, and global memory. Register tensors hold per-thread data, shared tensors are visible to all threads in a block, and global tensors are accessible by all blocks.
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Create a register tensor. |
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Allocate a shared tensor. |
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Allocate a global tensor. |
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Create a global tensor view. |
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Free a shared tensor. |
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Reshape a shared tensor. |
4.1.2. Load and Store¶
Transfer data between memory spaces. Load instructions copy data from global or shared memory into register tensors; store instructions write register data back.
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Load a slice of global tensor into a register tensor. |
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Store a register tensor into a slice of a global tensor. |
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Load a shared tensor into a register tensor. |
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Store a register tensor into a shared tensor. |
4.1.3. Asynchronous Copy (SM80+)¶
Copy data from global to shared memory asynchronously using the cp.async hardware path.
Operations are grouped with copy_async_commit_group and waited on with copy_async_wait_group.
For Hopper+ GPUs, prefer tma.global_to_shared which uses the TMA engine.
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Asynchronously copy a tile from global memory to shared memory. |
Commit async copies into a group. |
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Wait the completion of asynchronous copy groups. |
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Wait for all copy_async instructions to complete. |
4.1.4. Linear Algebra¶
Matrix multiplication using tensor cores. The dot instruction automatically selects the
appropriate MMA instruction based on the data types and GPU architecture. For explicit control
over Hopper or Blackwell tensor cores, use wgmma.mma or tcgen05.mma instead.
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Dot product. |
4.1.5. Elementwise Arithmetic¶
Per-element unary and binary operations on register tensors. All elementwise operations support
an optional out parameter to write results into an existing tensor, and binary operations
support NumPy-style broadcasting.
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Compute the element-wise absolute value. |
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Element-wise addition with broadcasting. |
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Clip element values to the range [min, max]. |
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Compute the element-wise natural exponential (e^x). |
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Compute the element-wise base-2 exponential (2^x). |
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Compute the element-wise natural logarithm (ln x). |
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Element-wise maximum with broadcasting. |
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Round each element to the nearest integer (round-to-nearest-even). |
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Compute the element-wise reciprocal square root (1/sqrt(x)). |
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Compute the element-wise square root. |
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Compute the element-wise square (x^2). |
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Select elements from |
4.1.6. Reduction¶
Reduce a register tensor along one or more dimensions. Each reduction supports dim to specify
which dimensions to reduce, keepdim to preserve the reduced dimension with size 1, and out
for in-place output.
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Test whether all elements are non-zero along the specified dimension(s). |
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Test whether any element is non-zero along the specified dimension(s). |
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Compute the maximum along the specified dimension(s). |
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Compute the minimum along the specified dimension(s). |
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Sum elements along the specified dimension(s). |
4.1.7. Transform¶
Reshape, reinterpret, or rearrange register tensor data without changing the underlying values.
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Assign the value of src tensor to dst tensor. |
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Cast a register tensor to a different data type. |
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Repeat elements of a register tensor along its dimensions. |
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Repeat elements of a register tensor along its dimensions. |
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Squeeze a dimension of a register tensor with size 1. |
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Transpose a 2-D register tensor. |
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Unsqueeze a dimension of a register tensor. |
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View register tensor with a different layout or data type. |
4.1.8. Synchronization¶
Synchronize threads within a block or across a cluster. sync is the block-level barrier
(equivalent to __syncthreads()). For cluster-wide synchronization, use self.cluster.sync().
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Perform a synchronization. |
4.1.9. Atomic and Semaphore¶
Inter-block synchronization using global memory semaphores. lock_semaphore spins until the
semaphore reaches a target value; release_semaphore sets it to signal other blocks. Both
must be called from a single thread (self.single_thread()).
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Lock semaphore with a specified value. |
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Release semaphore with a specified value. |
4.1.10. Miscellaneous¶
Compiler hints, debugging aids, and layout annotations.
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Compiler hint to assume a condition is true. |
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Assert a compile-time condition. |
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Annotate the layout of a register or shared tensor. |
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Fast integer division and modulo using precomputed magic multiplier. |
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Print a tensor with a message. |
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Print a formatted string. |
4.2. Instruction Groups¶
Instruction groups provide access to specialized hardware units. Each group is accessed as an
attribute of the script (e.g., self.tma.global_to_shared(...)).
4.2.1. Memory Barrier (self.mbarrier)¶
Mbarriers are synchronization primitives in shared memory that track pending arrivals and asynchronous transaction bytes (tx-count). They coordinate producer-consumer patterns in pipelined kernels, particularly with TMA and TCGEN05 async operations. See Script.mbarrier.
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Allocate and initialize one or more mbarriers in shared memory. |
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Arrive at a barrier. |
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Arrive at a barrier and declare expected asynchronous transaction bytes. |
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Arrive at barriers across multiple CTAs with expected async transactions. |
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Arrive at a peer CTA's barrier with expected async transactions. |
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Wait for a barrier phase to complete. |
4.2.2. Fence (self.fence)¶
Proxy fences ensure memory ordering between different memory access paths (generic proxy vs.
async proxy). Required when generic writes (e.g., store_shared) must be visible to async
reads (e.g., tma.shared_to_global). See Script.fence.
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Bidirectional async proxy fence. |
Unidirectional generic-to-async release proxy fence for shared memory. |
4.2.3. TMA (self.tma)¶
The Tensor Memory Accelerator (TMA) on Hopper+ GPUs performs asynchronous bulk data transfers between global and shared memory without occupying SM compute resources. Completion is tracked via mbarriers. See Script.tma.
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Asynchronously copy a tile from global memory to shared memory via TMA. |
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Asynchronously copy a tile from shared memory to global memory via TMA. |
Commit pending TMA async copy operations into a group. |
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Wait for TMA async copy commit groups to complete. |
4.2.4. WGMMA (self.wgmma)¶
Warp Group Matrix Multiply-Accumulate on Hopper GPUs. Executes asynchronous MMA using a warp group (4 warps, 128 threads) with operands in shared memory or registers. Requires a strict fence → mma → commit → wait protocol. See Script.wgmma.
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Issue a warp group MMA fence. |
Commit the previously issued warp group MMA operations. |
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Wait for warp group MMA commit groups to complete. |
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Perform warp group matrix multiply-accumulate (MMA) operation. |
4.2.5. TCGEN05 (self.tcgen05)¶
Tensor Core Generation 05 on Blackwell GPUs. Introduces tensor memory (TMEM) — a dedicated on-chip accumulator space for MMA operations. Supports the full TMEM lifecycle: allocation, data movement (load/store/copy), MMA compute, and deallocation. See Script.tcgen05.
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Allocate a tensor in tensor memory (TMEM). |
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Deallocate a tensor memory tensor. |
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Create a sliced view of a tensor memory tensor. |
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Reinterpret a tensor memory tensor with a different dtype and shape. |
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Relinquish the tensor memory allocation permit. |
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Load data from tensor memory into registers. |
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Store data from registers into tensor memory. |
Wait for all pending tensor memory load operations to complete. |
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Wait for all pending tensor memory store operations to complete. |
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Copy data from shared memory to tensor memory. |
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Commit pending tcgen05 async operations and signal an mbarrier. |
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Perform tensor core matrix multiply-accumulate with TMEM accumulator. |
4.2.6. Cluster (self.cluster)¶
Block cluster operations for multi-CTA coordination on Hopper+ GPUs. Provides cluster-wide synchronization, introspection (block index/rank within the cluster), and cross-CTA shared memory addressing. See Script.cluster.
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Synchronize all thread blocks in the current cluster. |
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Map shared memory address(es) to the corresponding address(es) in another CTA's shared memory. |
The block index within the cluster. |
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The linear rank of the current block within the cluster. |
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The dimensions of the cluster. |
4.2.7. CLC (self.clc)¶
Cluster Launch Control on Blackwell GPUs enables dynamic work scheduling by canceling not-yet-launched clusters. A scheduler CTA requests cancellation, then queries the result to take over the canceled cluster’s work. See Script.clc.
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Request cancellation of a cluster that has not yet been launched. |
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Query the response from a cluster launch control try_cancel operation. |