Glossary

NVIDIA- and compiler-specific terms used throughout these docs.

Term	Definition
ACF	Advanced Controls File — a file generated by CompileIQ (or curated in a Booster Pack) that is passed to a compiler via --apply-controls to change its optimization decisions for a specific kernel. See Tuning NVIDIA Compilers.
Batch Decode	A decode-phase attention workload pattern (e.g. FlashInfer’s BatchDecodeWithPagedKVCacheWrapper) that processes many sequences’ next-token generation in a single batched kernel call against a paged KV cache. See Applying a Booster Pack to FlashInfer.
compute capability / sm_XX	A version number (e.g. sm_90a, sm_100) identifying the set of features a GPU architecture supports. Passed to NVCC/PTXAS via -arch to target a specific GPU generation.
CTA	Cooperative Thread Array — CUDA’s term for a thread block, the group of threads that can synchronize and share memory on one streaming multiprocessor.
CTK	CUDA Toolkit — the NVIDIA SDK (compilers, libraries, tools) used to build and run CUDA programs. CompileIQ’s Advanced Controls Interface requires CTK 13.3 or newer.
cuTile	A tile-based CUDA programming model (also called CudaTile) for writing kernels in terms of tile-level operations rather than per-thread code. See Autotuning cuTile parameters.
FA / GQA / MHA / MLA	Common attention kernel variants: Flash Attention (FA), Grouped-Query Attention (GQA), Multi-Head Attention (MHA), and Multi-head Latent Attention (MLA). Referenced by the att (attention) compiler search-space variant.
FlashInfer	An open-source library of optimized attention/inference kernels for LLM serving, used as a target workload for the Helion Booster Pack.
Helion	A Python-embedded kernel authoring language and compiler that can consume ACFs through its own ACF API.
JIT	Just-in-time compilation — compiling a kernel at runtime (as opposed to ahead-of-time), which is how frameworks like Triton and Helion typically produce GPU code.
NVBench	A CUDA kernel benchmarking library that provides accurate, repeatable timing measurements. See Benchmarking.
NVCC	NVIDIA CUDA Compiler — the driver that compiles CUDA C/C++ source into PTX/SASS. One of the two compilers CompileIQ tunes. See Tuning NVCC.
PTX	Parallel Thread Execution — NVIDIA’s intermediate, GPU-architecture-independent assembly language that NVCC generates and PTXAS compiles further into SASS.
PTXAS	The PTX Assembler — compiles PTX into SASS for a specific GPU architecture. One of the two compilers CompileIQ tunes. See Tuning PTXAS.
SASS	Streaming ASSembly or Shader ASSembly — the native machine code that actually runs on an NVIDIA GPU, produced by PTXAS from PTX. Different ACFs can produce different SASS for the same kernel source.
TMA	Tensor Memory Accelerator — dedicated hardware on recent NVIDIA GPU architectures for asynchronous, bulk global-to-shared-memory data transfers, exposed as a tunable hint in some search spaces.
Triton	An open-source Python-embedded language and compiler for writing GPU kernels, which lowers to PTX and finally to SASS via PTXAS. See Tuning PTXAS in Triton.
XLA	Accelerated Linear Algebra — a domain-specific compiler for linear algebra used by frameworks like JAX and TensorFlow to lower computation graphs to GPU code.